Combining low-power scan testing and test data compression for system-on-a-chip

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 166-169

  Chandra, A ^a   Chakrabarty, K ^a  

^a Duke University   (United States)

Author keywords

Embedded core testing; Golomb codes; Precomputed test sets; Scan testing; Switching activity; Test set encoding

Indexed keywords

COMBINATORIAL CIRCUITS; DATA COMPRESSION; INTEGRATED CIRCUIT TESTING;

SYSTEM-ON-A-CHIP (SOC) DESIGN;

VLSI CIRCUITS;

EID: 0034846650     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378396     Document Type: Conference Paper

References (12)

1. A distributed BIST control scheme for complex VLSI devices
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3. Minimized power consumption for scan-based BIST
4. A test vector inhibiting technique for low energy BIST design
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6. Techniques for minimizing power dissipation in scan and combinational circuits during test application
7. Static compaction techniques to control scan vector power dissipation
8. Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip
9. A novel test methodology for core-based system LSIs and a testing time minimization problem
10. Test vector decompression via cyclical scan chains and its application to testing core-based design
11. System-on-a-chip test data compression and decompression architectures based on Golomb codes
12. Test set compaction algorithms for combinational circuits