An efficient test relaxation technique for combinational & full-scan sequential circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 53-59

  El Maleh, A ^a   Al Suwaiyan, A ^a  

^a KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

Author keywords

Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Compaction; Sequential analysis; Sequential circuits; System testing; Test pattern generators; Very large scale integration

Indexed keywords

AUTOMATIC TESTING; COMPACTION; DATA COMPRESSION; ELECTRIC NETWORK ANALYSIS; INTEGRATION TESTING; SEQUENTIAL CIRCUITS; SYSTEM-ON-CHIP; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; SEQUENTIAL ANALYSIS; SYSTEM TESTING; TEST PATTERN GENERATOR;

AUTOMATIC TEST PATTERN GENERATION;

EID: 48049122310     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011111     Document Type: Conference Paper

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