Constrained ATPG for broadside transition testing

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 175-182

  Liu, Xiao ^a   Hsiao, Michael S ^a  

^a Virginia Polytechnic Institute and State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; CRIME; DEFECTS; DESIGN FOR TESTABILITY; DYNAMIC RANDOM ACCESS STORAGE; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING;

BOOLEAN FORMULAE; BROADSIDE TRANSITION TESTING; TEST SETS; TRANSITION FAULTS; UNDESIRABLE STATE; YIELD LOSS;

FAULT DETECTION;

EID: 84971249871     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250110     Document Type: Conference Paper

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