Preferred fill: A scalable method to reduce capture power for scan based designs

Proceedings - International Test Conference

Volumn , Issue , 2006, Pages

  Remersaro, Santiago ^a   Lin, Xijiang ^b   Zhang, Zhuo ^a   Reddy, Sudhakar M ^a   Pomeranz, Irith ^c   Rajski, Janusz ^b  

^a UNIVERSITY OF IOWA   (United States)

^b MENTOR GRAPHICS CORPORATION   (United States)

^c PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POTENTIAL; FAULT DETECTION; POWER CONTROL; SCALABILITY; VECTORS;

SCAN BASED TESTS; SUPPLY CURRENT;

DESIGN FOR TESTABILITY;

EID: 39749136228     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2006.297694     Document Type: Conference Paper

References (27)