Techniques for minimizing power dissipation in scan and combinational circuits during test application

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 12, 1998, Pages 1325-1333

  Dabholkar, Vinay ^a   Chakravarty, Sreejit ^a   Pomeranz, Irith ^a   Reddy, Sudhakar ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

Power dissipation; Power minimization; Scan design; Test application

Indexed keywords

EID: 0001321331     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.736572     Document Type: Article

References (25)

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