On reducing peak current and power during test

Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Volumn , Issue , 2005, Pages 156-161

  Li, Wei ^a   Reddy, Sudhakar M ^a   Pomeranz, Irith ^b  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY FAULT TESTING; LAUNCH VECTORS; PEAK CURRENT; POWER DISSIPATION;

ELECTRIC FAULT CURRENTS; ELECTRIC LOSSES; ELECTRIC POWER SYSTEMS; ELECTRONIC EQUIPMENT TESTING; NETWORKS (CIRCUITS); VECTORS;

ELECTRIC CURRENTS;

EID: 26844493717     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. J. A. Waicukauski, E. Lindbloom, B. K. Rosen and V. S. Iyengar, "Transition Fault Simulation", IEEE Design & Test of Computers, Vol. 4, No. 2, April 1987.
2. G. L. Smith, "Model for Delay Faults Based Upon Paths", Proc. ITC, pp. 342-349, 1985
3. J. Saxena, et. al., "A Case Study of IR-Drop in Structured At-Speed Testing", Proc. ITC. pp. 1098-1104, 2003
4. V. Dabholkar, S. Chakravarty, I. Pomeranz and S. M. Reddy, "Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application", IEEE TCAD, pp. 1325-1333, 1998
5. S. Gerstendorfer and H. J. Wunderlich, "Minimized Power Consumption for Scan-based BIST', Proc. ITC, pp. 77-84, 1999
6. R. Sankaralingam, R. R. Oruganti and N. A. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation", Proc. VTS, pp. 35-40, 2000
7. S. Kajihara, K. Ishida and K. Miyase, "Test Vector Modification for Power Reduction during Scan Testing", Proc. VTS, pp. 160-165, 2002
8. A. Chandra and K. Chakrabarty, "Reduction of SOC Test Data Volume, Scan Power and Testing Time Using Alternating Run-length Codes", Proc. DAC, pp 673-678, 2002
9. P. Girard, L. Guiller, C. Landrault and S. Pravossoudovitch, "Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption", Proc. ATS, pp. 89-94, 1999
10. P. M. Rosinger, B. M. Al-Hashimi and N. Nicolici, "Scan Architecture for Shift and Capture Cycle Power Reduction", Proc. DFT, pp. 129-137, 2002
11. K. Lee, S. Hsu and C. Ho, "Test Power Reduction with Multiple Capture Orders", Proc. ATS, pp. 26-31, 2004
12. W. Li, S. M. Reddy and I. Pomeranz, "On Test Generation for Transition Faults with Minimized Peak Power Dissipation", Proc. DAC, pp. 504-509, 2004
13. H.Weste, K. Eshraghian, "Plinciples of CMOS VLSI Design: A System Perspective", 2nd ed.,MA:Addison-Wesley, 1992
14. K. M. Butler, et. al., "Minimizing Power Consumption in Scan Testing: Pattern Generation and DFT Techniques", Proc. ITC, pp 355-363, 2004