-
1
-
-
0015564343
-
Enhancing testability of large scale integrated circuits via test points and additional logic
-
M. J. Y. Williams and J. B. Angell, "Enhancing Testability of Large Scale Integrated Circuits via Test Points and Additional Logic", IEEE Trans. on Computers, 1973, pp. 46-60.
-
(1973)
IEEE Trans. on Computers
, pp. 46-60
-
-
Williams, M.J.Y.1
Angell, J.B.2
-
3
-
-
0023293294
-
Scan design using standard flip-flops
-
Feb.
-
S. M. Reddy and R. Dandapani, "Scan Design Using Standard Flip-Flops", IEEE Design & Test, Feb. 1987, pp. 52-54.
-
(1987)
IEEE Design & Test
, pp. 52-54
-
-
Reddy, S.M.1
Dandapani, R.2
-
4
-
-
0027869248
-
On selecting flip-flops for partial reset
-
M. Abramovici, P. S. Parikh, B. Mathew and D. G. Saab, "On Selecting Flip-Flops for Partial Reset", in Proc. Intl. Test Conf., 1993, pp. 1008-1012.
-
(1993)
Proc. Intl. Test Conf.
, pp. 1008-1012
-
-
Abramovici, M.1
Parikh, P.S.2
Mathew, B.3
Saab, D.G.4
-
5
-
-
0027309690
-
Non-scan design-for-testability techniques for sequential circuits
-
V. Chickermane, E. M. Rudnick, P. Banerjee and J. H. Patel, "Non-Scan Design-for-Testability Techniques for Sequential Circuits", in Proc. 30th Design Autom. Conf., 1993, pp. 236-241.
-
(1993)
Proc. 30th Design Autom. Conf.
, pp. 236-241
-
-
Chickermane, V.1
Rudnick, E.M.2
Banerjee, P.3
Patel, J.H.4
-
6
-
-
0029489282
-
On combining design for testability techniques
-
Oct.
-
P. Parikh and M. Abramovici, "On Combining Design for Testability Techniques", in Proc. 1995 Intl. Test Conf., Oct. 1995, pp. 423-429.
-
(1995)
Proc. 1995 Intl. Test Conf.
, pp. 423-429
-
-
Parikh, P.1
Abramovici, M.2
-
7
-
-
0029518837
-
Testable design of non-scan sequential circuits using extra logic
-
Nov.
-
D. K. Das and B. B. Bhattacharya, "Testable Design of Non-Scan Sequential Circuits using Extra Logic", in Proc. Asian Test Symp., Nov. 1995, pp. 176-182.
-
(1995)
Proc. Asian Test Symp.
, pp. 176-182
-
-
Das, D.K.1
Bhattacharya, B.B.2
-
8
-
-
0033906659
-
On the use of fully specified initial states for testing of synchronous sequential circuits
-
Feb.
-
I. Pomeranz and S. M. Reddy, "On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits", IEEE Trans. on Computers, Feb. 2000, pp. 175-182.
-
(2000)
IEEE Trans. on Computers
, pp. 175-182
-
-
Pomeranz, I.1
Reddy, S.M.2
-
9
-
-
0034480245
-
Non-scan design for testability for synchronous sequential circuits based on conflict analysis
-
X. Dong, X. Yi and H. Fujiwara, "Non-Scan Design for Testability for Synchronous Sequential Circuits Based on Conflict Analysis", in Proc. Intl. Test Conf., 2000, pp. 520-529.
-
(2000)
Proc. Intl. Test Conf.
, pp. 520-529
-
-
Dong, X.1
Yi, X.2
Fujiwara, H.3
-
10
-
-
0034275158
-
A new class of sequential circuits with combinational test generation complexity
-
Sept.
-
H. Fujiwara, "A New Class of Sequential Circuits with Combinational Test Generation Complexity", IEEE Trans. on Computers, Sept. 2000, pp. 895-905.
-
(2000)
IEEE Trans. on Computers
, pp. 895-905
-
-
Fujiwara, H.1
-
12
-
-
0035687353
-
Too much delay fault coverage is a bad thing
-
Oct.
-
J. Rearick, "Too Much Delay Fault Coverage is a Bad Thing", in Proc. Intl. Test Conf., Oct. 2001, pp. 624-633.
-
(2001)
Proc. Intl. Test Conf.
, pp. 624-633
-
-
Rearick, J.1
-
13
-
-
0024610491
-
A directed search method for test generation using concurrent simulator
-
Feb.
-
V. D. Agrawal, K. T. Cheng, and P. Agrawal, "A Directed Search Method for Test Generation Using Concurrent Simulator," IEEE Trans. on Computer-Aided Design, Feb. 1989, pp. 131-138.
-
(1989)
IEEE Trans. on Computer-aided Design
, pp. 131-138
-
-
Agrawal, V.D.1
Cheng, K.T.2
Agrawal, P.3
-
14
-
-
0029536659
-
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits
-
Dec.
-
S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits", IEEE Trans. on Computer-Aided Design, Dec. 1995, pp. 1496-1504.
-
(1995)
IEEE Trans. on Computer-aided Design
, pp. 1496-1504
-
-
Kajihara, S.1
Pomeranz, I.2
Kinoshita, K.3
Reddy, S.M.4
-
15
-
-
0035472563
-
Forward-looking fault simulation for improved static compaction
-
October
-
I. Pomeranz and S. M. Reddy, "Forward-Looking Fault Simulation for Improved Static Compaction", IEEE Trans. on Computer-Aided Design, October 2001, pp. 1262-1265.
-
(2001)
IEEE Trans. on Computer-aided Design
, pp. 1262-1265
-
-
Pomeranz, I.1
Reddy, S.M.2
-
16
-
-
0027667677
-
Classification of faults in synchronous sequential circuits
-
Sept.
-
I. Pomeranz and S. M. Reddy, "Classification of Faults in Synchronous Sequential Circuits", IEEE Trans. on Computers, Sept. 1993, pp. 1066-1077.
-
(1993)
IEEE Trans. on Computers
, pp. 1066-1077
-
-
Pomeranz, I.1
Reddy, S.M.2
|