Test power reduction with multiple capture orders

Proceedings of the Asian Test Symposium

Volumn , Issue , 2004, Pages 26-31

  Lee, Kuen Jong ^a   Hsu, Shaing Jer ^a   Ho, Chia Ming ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; ENERGY DISSIPATION; LOGIC DESIGN; PERFORMANCE;

CHAIN-BASED CIRCUITS; FAULT COVERAGE; SUB-CHAINS; TEST POWER;

MICROPROCESSOR CHIPS;

EID: 13244279379     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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9. T.H. Cormen, C.E. Leiserson, R.L. Rivest, and C. Stein, Introduction to Algorithms, McGraw-Hill, 2001.
10. H. Ueda and K. Kinoshita, "Low power design and its testability," In Proc. Asian Test Symp., 1995, pp. 361-366.
11. K.I. Diamantaras and N.K. Jha, "A New Transition Count Method for Testing of Logic Circuits," IEEE Trans. on CAD of Integrated Circuits and Systems, Mar. 1991, pp. 407-410.