Low-power scan design using first-level supply gating

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 3, 2005, Pages 384-395

  Bhunia, Swarup ^a   Mahmoodi, Hamid ^a   Ghosh, Debjyoti ^b   Mukhopadhyay, Saibal ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b ANALOG DEVICES INC   (United States)

Author keywords

Low power test; Scan design; Supply gating

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONSTRAINT THEORY; DIFFRACTION GRATINGS; ELECTRIC POTENTIAL; NATURAL FREQUENCIES; PORTABLE EQUIPMENT; TRANSISTORS;

AUTOMATIC TEST PATTERN GENERATION (ATPG); LOW POWER TEST; SCAN DESIGN; SIGNAL TRANSITION; SUPPLY GRATING;

SCANNING;

EID: 15844369074     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.842885     Document Type: Article

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