Reducing power dissipation during test using scan chain disable

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 319-324

  Sankaralingam, R ^a   Pouya, B ^a   Touba, N A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; AUTOMATIC TESTING; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY DISSIPATION; FAILURE ANALYSIS; FLIP FLOP CIRCUITS; LOGIC GATES; SWITCHING CIRCUITS;

AUTOMATIC TEST PATTERN GENERATION; POWER DISSIPATION; SCAN CHAINS;

INTEGRATED CIRCUIT TESTING;

EID: 0034995123     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)

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