Low-capture-power test generation for scan-based at-speed testing

Proceedings - International Test Conference

Volumn 2005, Issue , 2005, Pages 1019-1028

  Wen, Xiaoqing ^a   Yamashita, Yoshiyuki ^a   Morishima, Shohei ^a   Kajihara, Seiji ^a   Wang, Laung Terng ^b   Saluja, Kewal K ^c   Kinoshita, Kozo ^d  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b SYNTEST TECHNOLOGIES INC   (United States)

^c University of Wisconsin Madison   (United States)

^d OSAKA GAKUIN UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY DISSIPATION; ERROR DETECTION; RISK MANAGEMENT; SWITCHING CIRCUITS;

CIRCUIT MALFUNCTION; CIRCUIT SWITCHING ACTIVITY; SCAN-BASED AT-SPEED TESTING; TEST GENERATION; TEST QUALITY;

INTEGRATED CIRCUIT TESTING;

EID: 33845439960     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584068     Document Type: Conference Paper

References (28)

1. S. Savir and S. Paul, "On Broad-Side Delay Test," Proc. VLSI Test Symp., pp. 284-290, 1994.
2. X. Lin, R. Press, J. Rajski, P. Reuter, T. Rinderknecht, B. Swanson, and N. Tamarapalli, "High-Frequency, At-Speed Scan Testing," IEEE Design & Test of Computers, pp. 17-25, September-October, 2003.
3. J. Gatej, L. Song, C. Pyron, R. Raina, and T. Munns, "Evaluating ATE Features in Terms of Test Escape Rates and Other Cost of Test Culprits," Proc. Intl. Test Conf., pp. 1040-1048, 2002.
4. P. Nigh, D. Vallett, A. Patel, J. Wright, F. Motika, D. Forlenza, R. Kurtulik, and W. Chong, "Failure Analysis of Timing and IDDq-only Failures from the SEMATECH Test Methods Experiment ," Proc. Intl. Test Conf., pp. 43-52, 1998.
5. N. Tendolkar, R. Raina, R. Wellenberg, X. Lin, B. Swanson, and G. Aldrich, "Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC™ Instruction Set Architecture," Proc. VLSI Test Symp., pp. 3-8, 2002.
6. P. Girard, "Survey of Low-Power Testing of VLSI Circuits," IEEE Design & Test of Computers, vol. 19, no. 3, pp. 82-92, May/June 2002.
7. N. Nicolici and B. Al-Hashimi, Power-Constrained Testing of VLSI Circuits, Kluwer Academic Publishers, 2003.
8. Y. Zorian, "A Distributed BIST Control Scheme for Complex VLSI Devices," Proc. VLSI Test Symp., pp. 4-9, 1993.
9. R. Chou, K. Saluja, and V. Agrawal, "Scheduling Tests for VLSI Systems under Power Constraints," IEEE Trans. on VLSI Systems, vol. 5, no. 6, pp. 175-185, 1997.
10. S. Wang and S. Gupta, "ATPG for Heat Dissipation Minimization during Test Application," IEEE Trans. on Computers, vol. 47, no. 2, pp. 256-262, 1998.
11. F. Corno, P. Prinetto, M. Redaudengo, and M. Reorda, "A Test Pattern Generation Methodology for Low Power Consumption," Proc. VLSI Test Symp., pp. 35-40, 2000.
12. R. Sankaralingam, R. Oruganti, and N. Touba, "Static Compaction Techniques to Control Scan Vector Power Dissipation," Proc. VLSI Test Symp., pp. 35-40, 2000.
13. S. Kajihara, K. Ishida, and K. Miyase, "Test Vector Modification for Power Reduction during Scan Testing," Proc. VLSI Test Symp., pp. 160-165, 2002.
14. V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy, "Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits during Test Application," IEEE Trans. on Computer-Aided Design, vol. 17, no. 12, pp. 1325-1333, 1998.
15. A. Chandra and K. Chakrabarty, "Combining Low Power Scan testing and Test Data Compression for System-on-a-Chip," Proc. Design Automation Conf., pp. 166-169, 2001.
16. A. Chandra and K. Chakrabarty, "Reduction of SoC Test Data Volume, Scan Power and Testing Time Using Alternating RunLength Codes," Proc. Design Automation Conf., pp. 673-678, 2002.
17. A. Hertwig and H. Wunderlich, "Low Power Serial Built-in Self-Test," Proc. European Test Workshop, pp. 49-53, 1998.
18. R. Sankaralingam, R. Oruganti, and N. Touba, "Reducing Power Dissipation during Test Using Scan Chain Disable," Proc. VLSI Test Symp., pp. 319-324, 2001.
19. T. Yoshida and M. Watari, "MD-Scan Method for Low Power Scan Testing," Proc. Intl. Test Conf., pp. 480-487, 2003.
20. Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch "Power Driven Chaining of Flip-Flops in Scan Architectures," Proc. Intl. Test Conf., pp. 796-803, 2002.
21. J. Saxena, K. Butler, and L. Whetsel, "A Scheme to Reduce Power Consumption during Scan Testing," Proc. Intl. Test Conf., pp. 670-677, 2001.
22. O. Sinanoglu and A. Orailoglu, "Scan Power Minimization through Stimulus and Response Transformations," Proc. Design, Automation and Test in Europe, pp. 404-409, 2004.
23. S. Gerstendoerfer and H. Wunderlich, "Minimized Power Consumption for Scan-Based BIST," Proc. Intl. Test Conf., pp. 77-84, 1999.
24. S. Wang, "Generation of Low-Power-Dissipation and High-Fault Coverage Patterns for Scan-Based BIST," Proc. Intl. Test Conf., pp. 834-843, 2002.
25. J. Saxena, K. M. Butler, V. B. Jayaram, and S. Kundu, "A Case Study of IR-Drop in Structured At-Speed Testing," Proc. Intl. Test Conf., pp. 1098-1104, 2003.
26. K. Lee, T. Huang, and J. Chen, "Peak-Power Reduction for Multiple-Scan Circuits during Test Application," Proc. Asian Test Symp., pp. 435-440, 2000.
27. R. Sankaralingam and N. A. Touba, "Controlling Peak Power During Scan Testing," Proc. VLSI Test Symp., pp. 153-159, 2002.
28. X. Wen, H. Yamashita, S. Kajihara, L.-T. Wang, K. Saluja, and K. Kinoshita, "On Low-Capture-Power Test Generation for Scan Testing," Proc. VLSI Test Symp., pp. 265-270, 2005.