On generating pseudo-functional delay fault tests for scan designs

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2005, Pages 398-405

  Zhang, Zhuo ^a   Reddy, Sudhakar M ^a   Pomeranz, Irith ^b  

^a UNIVERSITY OF IOWA   (United States)

^b PURDUE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

POWER DISSIPATION; PSEUDO-FUNCTIONAL DELAY FAULT TEST;

ELECTRIC CURRENTS; ENERGY DISSIPATION; INTEGRATED CIRCUITS; SCANNING;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 28444443346     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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