Scan power minimization through stimulus and response transformations

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 404-409

  Sinanoglu, Ozgur ^a   Orailoglu, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFORMATION; SHIFT CYCLES; STIMULUS; SYSTEM-ON-CHIP (SOC); MINIMAL AREA; POWER THRESHOLDS; SCAN CELLS; SCAN CHAIN; SCAN POWER; SWITCHING ACTIVITIES; TEST VECTORS;

ALGEBRA; ALGORITHMS; BENCHMARKING; COST EFFECTIVENESS; LOGIC GATES; MATHEMATICAL TRANSFORMATIONS; MATRIX ALGEBRA; VECTORS; DESIGN; EXHIBITIONS; INTEGRATED CIRCUIT TESTING; PROGRAMMABLE LOGIC CONTROLLERS;

COMPUTER SCIENCE; LINEAR TRANSFORMATIONS;

EID: 3042565475     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268880     Document Type: Conference Paper

References (16)

1. H. J. Wunderlich and S. Gerstendorfer, "Minimized power consumption for scan based BIST", in ITC, pp. 85-94, 1999.
2. R. Sankaralingam and N.A. Touba, "Inserting Test Points to Control Peak Power During Scan Testing", in DFT, pp. 138-146, 2002.
3. T. Huang and K. Lee, "An input control technique for power reduction in scan circuits during test application", in ATS, pp. 315-320, 1999.
4. N. Nicolici, B. M. Al-Hashimi and A. C. Williams, "Minimisation of power dissipation during test application in full-scan sequential circuits using primary input freezing", IEEE TCOMP, vol. 47, n. 2, pp. 256-262, 1998.
5. L. Whetsel, "Adapting scan architectures for low power operation", in ITC, pp. 863-872, 2000.
6. Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch and H.J. Wunderlich, "A modified clock scheme for a low power BIST test pattern generator", in VTS, pp. 306-311, 2001.
7. V. Dabholkar, S. Chakravarty, I. Pomeranz and S. M. Reddy, "Techniques for minimizing power dissipation in scan and combinational circuits during test application", IEEE TCAD, vol. 17, n. 12, pp. 1325-1333, 1998.
8. R. Sankaralingam, R. R. Oruganti and N. A. Touba, "Adapting scan architectures for low power operation", in VTS, pp. 35-40, 2000.
9. R. Sankaralingam, B. Pouya and N.A. Touba, "Reducing Power Dissipation During Test Using Scan Chain Disable", in VTS, pp. 319-324, 2001.
10. O. Sinanoglu, I. Bayraktaroglu and A. Orailoglu, "Test Power Reduction Through Minimization of Scan Chain Transitions", in VTS, pp. 166-171, 2002.
11. O. Sinanoglu, I. Bayraktaroglu and A. Orailoglu, "Scan Power Reduction Through Test Data Transition Frequency Analysis", in ITC, pp. 844-850, 2002.
12. O. Sinanoglu, I. Bayraktaroglu and A. Orailoglu, "Reducing Average and Peak Test Power Through Scan Chain Modification", JETTA, vol. 19, n. 4, pp. 457-467, 2003.
13. O. Sinanoglu and A. Orailoglu, "Modeling Scan Chain Modifications for Scan-in Test Power Minimization", in ITC, 2003.
14. O. Sinanoglu and A. Orailoglu, "Aggressive Test Power Reduction Through Test Stimuli Transformation", in ICCD, 2003.
15. G. W. Stewart, Introduction to Matrix Computations, Academic Press, 1973.
16. H. K. Lee and D. S. Ha, On the Generation of Test Patterns for Combinational Circuits, Technical Report 12-93, Department of Electrical Eng., Virginia Polytechnic Institute and State University.