A new ATPG method for efficient capture power reduction during scan testing

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 58-63

  Wen, Xiaoqing ^a   Kajihara, Seiji ^a   Miyase, Kohei ^b   Suzuki, Tatsuya ^a   Saluja, Kewal K ^c   Wang, Laung Terng ^d   Abdel Hafez, Khader S ^d   Kinoshita, Kozo ^e  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b JAPAN SCIENCE AND TECHNOLOGY AGENCY   (Japan)

^c University of Wisconsin Madison   (United States)

^d SYNTEST TECHNOLOGIES INC   (United States)

^e OSAKA GAKUIN UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; ELECTRIC FAULT CURRENTS; ENERGY DISSIPATION; PROBLEM SOLVING;

POWER DISSIPATION; POWER REDUCTION; TEST VECTOR; X-FILLING;

FLIP FLOP CIRCUITS;

EID: 33751104777     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.8     Document Type: Conference Paper

References (12)

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