A low power pseudo-random BIST technique

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 468-473

  Basturkmen, Nadir Z ^a   Reddy, Sudhakar M ^a   Pomeranz, Irith ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; FAILURE ANALYSIS; INTEGRATED CIRCUIT LAYOUT; PROBABILITY; SWITCHING CIRCUITS; TIMING CIRCUITS;

SCAN CHAIN DISABLE; SCAN CHAIN STRUCTURE; SWITCHING ACTIVITY;

BUILT-IN SELF TEST;

EID: 0036395397     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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