Too much delay fault coverage is a bad thing

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 624-633

  Rearick, Jeff ^a  

^a AGILENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; DESIGN FOR TESTABILITY; LOGIC CIRCUITS;

DELAY FAULT TESTS;

INTEGRATED CIRCUIT TESTING;

EID: 0035687353     PISSN: None     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966682     Document Type: Article

References (11)

1. Fastpath: A path-delay test generator for standard scan designs
2. Design for testability: Using scanpath techniques for path-delay test and measurement
3. Skewed-load transition test: Part I, calculus
4. Skewed-load transition test: Part II, coverage
5. Arrangement of latches in scan-path design to improve delay fault coverage
6. On broad-side delay test
7. On delay fault testing in logic circuits
8. Delay-fault test generation and synthesis for testability under a standard scan design methodology
9. Comparing functional and structural tests
10. Effective path selection for delay fault testing of sequential circuits
11. Combinational profiles of sequential benchmark circuits