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Volumn , Issue , 2004, Pages 355-364

Minimizing power consumption in scan testing: Pattern generation and DFT techniques

Author keywords

[No Author keywords available]

Indexed keywords

PATH DELAY FAULTS; PATTERN GENERATION; POWER REDUCTION; SCAN TESTING;

EID: 18144367021     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (257)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.