FinFET—A self-aligned double-gate MOSFET scalable to 20 nm

IEEE Transactions on Electron Devices

Volumn 47, Issue 12, 2000, Pages 2320-2325

  Hisamoto, Digh ^a   Lee, Wen Chin ^b   Kedzierski, Jakub ^b   Takeuchi, Hideki ^b   Asano, Kazuya ^b   Kuo, Charles ^b   Anderson, Erik ^c   King, Tsu Jae ^b   Jeffrey, Jeffrey ^b   Hu, Chenming ^b  

^a HITACHI LTD   (Japan)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c LAWRENCE BERKELEY NATIONAL LABORATORY   (United States)

Author keywords

Fully depleted soi; MOSFET; Poly sige; Short channel effect

Indexed keywords

EID: 29044440093     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.887014     Document Type: Article

References (13)

1. D. J. Frank, S. E. Laux, and M. V. Fischetti, "Monte carlo simulation of a 30 nm dual-gate MOSFET: How short can Si go?," in IEDM Tech. Dig.. 1992, pp. 553-556.
2. C. Fiegna et al., "A new scaling methodology for the 0.1-0.025 um MOSFET," in VLSI Symp. Tech. Dig.. 1993, pp. 33-34.
3. K. Suzuki et al, "Scaling theory for double-gate SOI MOSFET's," IEEE Trans. Electron Devices, vol. 40, pp. 2326-2329, 1993.
4. H. S. Wong, D. J. Frank, Y. Taur, and J. M. C. Stork, "Design and performance considerations for Sub0.1 urn double-gate SOI MOSFET's," in IEDM Tech. Dig.. 1994, pp. 747-750.
5. B. Majkusiak, T. Janik, and J. Walczak, "Semiconductor thickness effects in the double-gate SOI MOSFET," IEEE Trans. Electron Devices. vol. 45, pp. 1127-1134, May 1998.
6. L. T. Su, M. J. Sherony, H. Hu, J. E. Chung, and D. A. Antoniadis, "Optimization of series resistance in Sub0.2 urn SOI MOSFETs," in IEDM Tech. Dig.. 1993, pp. 723-726.
7. D. Hisamoto et al, "Metallized ultra-shallow-junction device technology for Sub0.1 urn gate MOSFET's," IEEE Trans. Electron Devices. vol. 41, pp. 745-750, May 1994.
8. J. Hwang and G. Pollack, "Novel polysilicon/TiN stacked-gate structure for fully-depleted SOI/CMOS," IEDM Tech. Dig., pp. 345-348, 1992.
9. D. Hisamoto et al., "A folded-channel MOSFET for deep-Subtenth micron era," IEDM Tech. Dig., pp. 1032-1034, 1998.
10. D. Hisamoto, T. Kaga, andE. Takeda, "Impact of the vertical SOI 'Delta' structure on planar device technology," IEEE Trans. Electron Devices, vol. 38, pp. 1419-1424, 1991.
11. S. Kimura, H. Noda, D. Hisamoto, and E. Takeda, "A 0.1 μm-gate elevated source and drain MOSFET fabricated by phase-shifted lithography," in IEDM Tech. Dig.. 1991, pp. 950-952.
12. T. Ushiki et al.. "Reliable tantalum gate fully-depleted-SOI MOSFET's with 0.15 //m gate length by low-temperature processing below 500 C," in IEDM Tech. Dig.. 1996, pp. 117-120.
13. T.-J. King, J. P. McVittie, K. C. Saraswat, and J. R. Pfiester, "Electrical properties of heavily doped polycrystalline silicon-germanium films," IEEE Trans. Electron Devices, vol. 41, pp. 228-232, Feb. 1994.