Challenges in gate stack engineering

Solid State Technology

Volumn 46, Issue 10, 2003, Pages 43-44+46+48

  Murto, Robert W ^a   Gardner, Mark I ^a   Brown, George A ^a   Zeitzoff, Peter M ^a   Huff, Howard R ^a  

^a SEMATECH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRON TUNNELING; LEAKAGE CURRENTS; MOSFET DEVICES; PERMITTIVITY; POLYSILICON; THRESHOLD VOLTAGE; VOLTAGE CONTROL;

DIRECT TUNNELING CURRENT; EQUIVALENT OXIDE THICKNESS; FRONT END PROCESS;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0142167993     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (17)

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