Performance benchmarking and effective channel length for nanoscale InAs, In0.53Ga0.47As, and sSi n-MOSFETs

IEEE Transactions on Electron Devices

Volumn 61, Issue 6, 2014, Pages 2027-2034

  Lizzit, Daniel ^a   Esseni, David ^a   Palestri, Pierpaolo ^a   Osgnach, Patrik ^a   Selmi, Luca ^a  

^a UNIVERSITY OF UDINE   (Italy)

Author keywords

device simulation; drain induced barrier lowering (DIBL); effective channel length; III V; Monte Carlo; strained Si (sSi); subthreshold swing (SS).

Indexed keywords

BENCHMARKING; GALLIUM; MONTE CARLO METHODS; NANOTECHNOLOGY; SILICON;

DEVICE SIMULATIONS; DRAIN-INDUCED BARRIER LOWERING; EFFECTIVE CHANNEL LENGTH; III-V; STRAINED SI (SSI); SUB-THRESHOLD SWING(SS);

MOSFET DEVICES;

EID: 84901363412     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2014.2315919     Document Type: Article

References (52)

1. M. Radosavljevic et al., "Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gateto- drain/gate-to-source separation for low power logic applications," in IEEE IEDM Tech. Dig., Dec. 2010, pp. 6.1.1-6.1.4.
2. G. Dewey, B. Chu-Kung, R. Kotlyar, M. Metz, N. Mukherjee, and M. Radosavljevic, "III-V field effect transistors for future ultra-low power applications," in IEEE Symp. VLSI Technol. Tech. Dig., Jun. 2012, pp. 45-46.
3. G. Doornbos and M. Passlack, "Benchmarking of III-V n-MOSFET maturity and feasibility for future CMOS," IEEE Electron Device Lett., vol. 31, no. 10, pp. 1110-1112, Oct. 2010.
4. M. Luisier, "Performance comparison of GaSb, strained-Si, and InGaAs double-gate ultrathin-body n-FETs," IEEE Electron Device Lett., vol. 32, no. 12, pp. 1686-1688, Dec. 2011.
5. S. H. Park et al., "Performance comparisons of III-V and strained-Si in planar FETs and nonplanar FinFETs at ultrashort gate length 12 nm," IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2107-2114, Aug. 2012.
6. M. De Michielis, D. Esseni, and F. Driussi, "Analytical models for the insight into the use of alternative channel materials in ballistic nano- MOSFETs," IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 115-123, Jan. 2007. (Pubitemid 46056049)
7. C.-H. Yu, Y.-S. Wu, V.-H. Hu, and P. Su, "Impact of quantum confinement on subthreshold swing and electrostatic integrity of ultra-thin-body GeOI and InGaAs-OI n-MOSFETs," IEEE Trans. Nanotechnol., vol. 11, no. 2, pp. 287-291, Mar. 2012.
8. K. Kalna, N. Seoane, A. J. García-Loureiro, I. G. Thayne, and A. Asenov, "Benchmarking of scaled InGaAs implant-free nanoMOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 9, pp. 2297-2306, Sep. 2008.
9. E. A. Towie, C. Riddet, and A. Asenov, "Comparison of raised source/drain implant-free quantum-well and tri-gate MOSFETs using 3D Monte Carlo simulation," in Proc. SISPAD, 2013, pp. 384-387.
10. Y. Xuan, Y. Wu, T. Shen, T. Yang, and P. Ye, "High performance submicron inversion-type enhancement-mode InGaAs MOSFETs with ALD Al2O3, HfO2 and HfAlO as gate dielectrics," in IEEE IEDM Tech. Dig., Dec. 2007, pp. 637-640.
11. C. Hinkle, A. Sonnet, R. Chapman, and E. M. Vogel, "Extraction of the effective mobility of In0.53Ga0.47As MOSFETs," IEEE Electron Device Lett., vol. 30, no. 4, pp. 316-318, Apr. 2009.
12. N. Taoka et al., "Impact of Fermi level pinning inside conduction band on electron mobility of InxGa1-x-As MOSFETs and mobility enhancement by pinning modulation," in IEEE IEDM Tech. Dig., Jul. 2011, pp. 27.2.1-27.2.4.
13. L. Lucci, P. Palestri, D. Esseni, L. Bergagnini, and L. Selmi, "Multisubband Monte Carlo study of transport, quantization, and electron-gas degeneration in ultrathin SOI n-MOSFETs," IEEE Trans. Electron Devices, vol. 54, no. 5, pp. 1156-1164, May 2007. (Pubitemid 46691568)
14. P. Osgnach, A. Revelant, D. Lizzit, P. Palestri, D. Esseni, and L. Selmi, "Toward computationally efficient multi-subband Monte Carlo simulations of nanoscale MOSFETs," in Proc. SISPAD, 2013, pp. 176-179.
15. P. Toniutti, P. Palestri, D. Esseni, F. Driussi, M. De Michielis, and L. Selmi, "On the origin of the mobility reduction in n- and p-metal- oxide-semiconductor field effect transistors with hafnium-based/metal gate stacks," J. Appl. Phys., vol. 112, no. 3, pp. 034502-1-034502-12, Aug. 2012.
16. D. Lizzit, P. Palestri, D. Esseni, A. Revelant, and L. Selmi, "Analysis of the performance of n-type FinFETs with strained SiGe channel," IEEE Trans. Electron Devices, vol. 60, no. 6, pp. 1884-1891, Jun. 2013.
17. P. Toniutti, D. Esseni, and P. Palestri, "Failure of the scalar dielectric function approach for the screening modeling in double-gate SOI MOSFETs and in FinFETs," IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 3074-3083, Nov. 2010.
18. F. Conzatti et al., "Investigation of strain engineering in FinFETs comprising experimental analysis and numerical simulations," IEEE Trans. Electron Devices, vol. 58, no. 6, pp. 1583-1593, Jun. 2011.
19. K. Cantley, Y. Liu, H. Pal, T. Low, S. Ahmed, and M. Lundstrom, "Performance analysis of III-V materials in a double-gate nano- MOSFET," in Proc. IEEE IEDM, Dec. 2007, pp. 113-116.
20. S. Jin, M. Fischetti, and T.-W. Tang, "Modeling of electron mobility in gated silicon nanowires at room temperature: Surface roughness scattering, dielectric screening, and band nonparabolicity," J. Appl. Phys., vol. 102, no. 8, pp. 083715-1-083715-14, 2007.
21. T. B. Bahder, "Eight-band k·p model of strained zinc-blende crystals," Phys. Rev. B, vol. 41, pp. 11992-12001, Jun. 1990.
22. R. Dittrich and W. Schroeder, "Empirical pseudopotential band structure of In0.53Ga0.47As and In0.52Al0.48As," Solid-State Electron., vol. 43, no. 2, pp. 403-407, 1999.
23. Y.-S. Kim, M. Marsman, G. Kresse, F. Tran, and P. Blaha, "Towards efficient band structure and effective mass calculations for III-V direct band-gap semiconductors," Phys. Rev. B, vol. 82, p. 205212, Nov. 2010.
24. D. Esseni, P. Palestri, and L. Selmi, Nanoscale MOS Transistors- Semi-Classical Transport and Applications, 1st ed. Cambridge, U.K.: Cambridge Univ. Press, 2011.
25. I. Vurgaftman, J. R. Meyer, and L. R. Ram-Mohan, "Band parameters for III-V compound semiconductors and their alloys," J. Appl. Phys., vol. 89, no. 11, pp. 5815-5875, 2001. (Pubitemid 33599303)
26. K. Kalna, S. Roy, A. Asenov, K. Elgaid, and I. Thayne, "Scaling of pseudomorphic high electron mobility transistors to decanano dimensions," Solid-State Electron., vol. 46, no. 5, pp. 631-638, 2002. (Pubitemid 34207608)
27. T. Oregan, M. Fischetti, B. Soree, S. Jin, W. Magnus, and M. Meuris, "Calculation of the electron mobility in III-V inversion layers with high- κ dielectrics," J. Appl. Phys., vol. 108, no. 10, pp. 103705-1-103705-11, 2010.
28. H. Pal, T. Low, and M. Lundstrom, "NEGF analysis of InGaAs Schottky barrier double gate MOSFETs," in IEEE IEDM Tech. Dig., Dec. 2008, pp. 1-4.
29. K. Majumdar, P. Majhi, N. Bhat, and R. Jammy, "HFinFET: A scalable, high performance, low leakage hybrid n-channel FET," IEEE Trans. Nanotechnol., vol. 9, no. 3, pp. 342-344, May 2010.
30. D. Rideau et al., "Strained Si, Ge, and Si1-xGex alloys modeled with a first-principles-optimized full-zone k·p method," Phys. Rev. B, vol. 74, p. 195208, Nov. 2006.
31. C. Jungemann, A. Edmunds, and W. L. Engl, "Simulation of linear and nonlinear electron transport in homogeneous silicon inversion layers," Solid-State Electron., vol. 36, no. 11, pp. 1529-1540, 1993. (Pubitemid 23706929)
32. M. V. Fischetti and S. E. Laux, "Monte Carlo study of electron transport in silicon inversion layers," Phys. Rev. B, vol. 48, pp. 2244-2274, Jul. 1993.
33. D. Esseni, "On the modeling of surface roughness limited mobility in SOI MOSFETs and its correlation to the transistor effective field," IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 394-401, Mar. 2004.
34. M. Poljak, V. Jovanović, D. Grgec, and T. Suligoj, "Assessment of electron mobility in ultrathin-body InGaAs-on-insulator MOSFETs using physics-based modeling," IEEE Trans. Electron Devices, vol. 59, no. 6, pp. 1636-1643, Jun. 2012.
35. D. Lizzit, D. Esseni, P. Palestri, and L. Selmi, "Surface roughness limited mobility modeling in ultra-thin SOI and quantum well III-V MOSFETs," in IEEE IEDM Tech. Dig., Dec. 2013, pp. 5.2.1-5.2.4.
36. T.-W. Kim et al., "ETB-QW InAs MOSFET with scaled body for improved electrostatics," in IEEE IEDM Tech. Dig., Dec. 2012, pp. 32.3.1-32.3.4.
37. K. Takei et al., "Quantum confinement effects in nanoscale-thickness InAs membranes," Nano Lett., vol. 11, no. 11, pp. 5008-5012, 2011.
38. N. Serra and D. Esseni, "Mobility enhancement in strained n-FinFETs: Basic insight and stress engineering," IEEE Trans. Electron Devices, vol. 57, no. 2, pp. 482-490, Feb. 2010.
39. F. Conzatti, M. Pala, D. Esseni, E. Bano, and L. Selmi, "Strain-induced performance improvements in InAs nanowire tunnel FETs," IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2085-2092, Aug. 2012.
40. M.-H. Na, E. Nowak, W. Haensch, and J. Cai, "The effective drive current in CMOS inverters," in IEEE IEDM Tech. Dig., Dec. 2002, pp. 121-124.
41. J. Deng and H.-S. Wong, "Metrics for performance benchmarking of nanoscale Si and carbon nanotube FETs including device nonidealities," IEEE Trans. Electron Devices, vol. 53, no. 6, pp. 1317-1322, Jun. 2006. (Pubitemid 43834530)
42. A. Alian et al., "Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices," in IEEE IEDM Tech. Dig., Dec. 2013, pp. 16.6.1-16.6.4.
43. S. Chang et al., "InAs N-MOSFETs with record performance of Ion = 600 μA/μm at Ioff = 100 nA/μm (Vd = 0.5 V)," in IEEE IEDM Tech. Dig., Dec. 2013, pp. 16.1.1-16.1.4.
44. Y. Taur, "MOSFET channel length: Extraction and interpretation, " IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 160-170, Jan. 2000. (Pubitemid 30565149)
45. L. Selmi, R. Menozzi, P. Gandolfi, and B. Riccó, "Numerical analysis of the gate voltage dependence of the series resistances and effective channel length in submicrometer GaAs MESFETs," IEEE Trans. Electron Devices, vol. 39, no. 9, pp. 2015-2020, Sep. 1992. (Pubitemid 23586031)
46. Y. Liu, M. Luisier, A. Majumdar, D. Antoniadis, and M. Lundstrom, "On the interpretation of ballistic injection velocity in deeply scaled MOSFETs," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 994-1001, Apr. 2012.
47. P. Lugli and D. Ferry, "Degeneracy in the ensemble Monte Carlo method for high-field transport in semiconductors," IEEE Trans. Electron Devices, vol. 32, no. 11, pp. 2431-2437, Nov. 1985. (Pubitemid 16539295)
48. P. Palestri, L. Lucci, S. D. Tos, D. Esseni, and L. Selmi, "An improved empirical approach to introduce quantization effects in the transport direction in multi-subband Monte Carlo simulations," Semicond. Sci. Technol., vol. 25, no. 5, pp. 055011-1-055011-10, 2010.
49. T. Dutta et al., "Origins of the short channel effects increase in III-V nMOSFET technologies," in Proc. 13th Int. Conf. ULIS, 2012, pp. 5-28.
50. Z. Lun, D. Ang, and C. Ling, "A novel subthreshold slope technique for the extraction of the buried-oxide interface trap density in the fully depleted SOI MOSFET," IEEE Electron Device Lett., vol. 21, no. 8, pp. 411-413, Aug. 2000.
51. S. Kim et al., "Strained In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors with epitaxial based biaxial strain," Appl. Phys. Lett., vol. 100, no. 19, p. 193510, 2012.
52. L. Xia and J. del Alamo, "Mobility enhancement in indium-rich N-channel InxGa1-xAs HEMTs by application of uniaxial strain," in Proc. Int. Conf. IPRM, 2010, pp. 1-4.