Performance comparisons of III-V and strained-Si in planar FETs and nonplanar FinFETs at ultrashort gate length (12 nm)

IEEE Transactions on Electron Devices

Volumn 59, Issue 8, 2012, Pages 2107-2114

  Park, Seung Hyun ^a   Liu, Yang ^b   Kharche, Neerav ^c   Salmani Jelodar, Mehdi ^a   Klimeck, Gerhard ^a   Lundstrom, Mark S ^a   Luisier, Mathieu ^d  

^a PURDUE UNIVERSITY   (United States)

^b IBM RESEARCH   (United States)

^c RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^d ETH ZURICH   (Switzerland)

Author keywords

Double gate; finFETs; III V versus Si; InGaAs; metal oxide semiconductor FETs; real space effective mass simulations; single gate; strained Si; triple gate

Indexed keywords

DOUBLE GATE; EFFECTIVE MASS; FINFETS; INGAAS; METAL OXIDE SEMICONDUCTOR; SINGLE GATES; STRAINED-SI; TRIPLE-GATE;

ARCHITECTURE; BALLISTICS; GALLIUM; INDIUM; INTEGRATED CIRCUITS; MOS DEVICES; MOSFET DEVICES; NANOTECHNOLOGY; QUANTUM ELECTRONICS; SILICON; THREE DIMENSIONAL;

SEMICONDUCTING SILICON;

EID: 84864767134     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2198481     Document Type: Article

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