-
1
-
-
84885448511
-
The use and abuse of large-scale brain models
-
C. Eliasmith and O. Trujillo "The use and abuse of large-scale brain models," Current Opinion Neurobiol. vol. 25 pp. 1-6 2014.
-
(2014)
Current Opinion Neurobiol
, vol.25
, pp. 1-6
-
-
Eliasmith, C.1
Trujillo, O.2
-
2
-
-
84870209909
-
A large-scale model of the functioning brain
-
Nov
-
C. Eliasmith T. C. Stewart X. Choo T. Bekolay T. DeWolf Y. Tang C. Tang and D. Rasmussen "A large-scale model of the functioning brain," Science vol. 338 no. 6111 pp. 1202-1205 Nov. 2012.
-
(2012)
Science
, vol.338
, Issue.6111
, pp. 1202-1205
-
-
Eliasmith, C.1
Stewart, T.C.2
Choo, X.3
Bekolay, T.4
Dewolf, T.5
Tang, Y.6
Tang, C.7
Rasmussen, D.8
-
3
-
-
79952309760
-
Scaling of brain metabolism with a fixed energy budget per neuron: Implications for neuronal activity plasticity and evolution
-
S. Herculano-Houzel "Scaling of brain metabolism with a fixed energy budget per neuron: Implications for neuronal activity plasticity and evolution," PLoS One vol. 6 no. 3 2011 e17514.
-
(2011)
PLoS One
, vol.6
, Issue.3
-
-
Herculano-Houzel, S.1
-
4
-
-
84861414911
-
The human brain project
-
May
-
H. Markram "The human brain project," Sci. Amer. vol. 306 no. 6 pp. 50-55 May 2012.
-
(2012)
Sci. Amer
, vol.306
, Issue.6
, pp. 50-55
-
-
Markram, H.1
-
5
-
-
79251488149
-
The tops in flops
-
Feb
-
P. Kogge "The tops in flops," IEEE Spectrum vol. 48 no. 2 pp. 48-54 Feb. 2011.
-
(2011)
IEEE Spectrum
, vol.48
, Issue.2
, pp. 48-54
-
-
Kogge, P.1
-
6
-
-
84887947383
-
Overview of the SpiNNaker system architecture
-
Dec
-
S. B. Furber D. R. Lester L. A. Plana J. D. Garside E. Painkras S. Temple and A. D. Brown "Overview of the SpiNNaker system architecture," IEEE Trans. Comput. vol. 62 no. 12 pp. 2454-2467 Dec. 2013.
-
(2013)
IEEE Trans. Comput
, vol.62
, Issue.12
, pp. 2454-2467
-
-
Furber, S.B.1
Lester, D.R.2
Plana, L.A.3
Garside, J.D.4
Painkras, E.5
Temple, S.6
Brown, A.D.7
-
7
-
-
84900504664
-
The SpiNNaker project: A massively-parallel computer architecture for neural simulations
-
May DOI: 10.1109/JPROC.2014. 2304638
-
S. B. Furber F. Gallupi S. Temple and L. A. Plana "The SpiNNaker project: A massively-parallel computer architecture for neural simulations," Proc. IEEE vol. 102 no. 5 May 2014 DOI: 10.1109/JPROC.2014. 2304638.
-
(2014)
Proc. IEEE
, vol.102
, Issue.5
-
-
Furber, S.B.1
Gallupi, F.2
Temple, S.3
Plana, L.A.4
-
10
-
-
35948993879
-
Neurotech for neuroscience: Unifying concepts organizing principles emerging tools
-
R. Silver K. Boahen S. Grillner N. Kopell and K. L. Olsen "Neurotech for neuroscience: Unifying concepts organizing principles emerging tools," J. Neurosci. vol. 27 no. 44 pp. 11807-11819 2007.
-
(2007)
J. Neurosci
, vol.27
, Issue.44
, pp. 11807-11819
-
-
Silver, R.1
Boahen, K.2
Grillner, S.3
Kopell, N.4
Olsen, K.L.5
-
11
-
-
0025507283
-
Neuromorphic electronic systems
-
Oct
-
C.Mead "Neuromorphic electronic systems," Proc. IEEE vol. 78 no. 10 pp. 1629-1636 Oct. 1990.
-
(1990)
Proc. IEEE
, vol.78
, Issue.10
, pp. 1629-1636
-
-
Mead, C.1
-
16
-
-
84880823556
-
Design of silicon brains in the nano-CMOS era: Spiking neurons learning synapses and neural architecture optimization
-
A. S. Cassidy J. Georgiou and A. G. Andreou "Design of silicon brains in the nano-CMOS era: Spiking neurons learning synapses and neural architecture optimization," Neural Netw. vol. 45 pp. 4-26 2013.
-
(2013)
Neural Netw
, vol.45
, pp. 4-26
-
-
Cassidy, A.S.1
Georgiou, J.2
Andreou, A.G.3
-
18
-
-
34250901737
-
A heteroassociative memory using current-mode MOS analog VLSI circuits
-
May
-
K. A. Boahen P. O. Pouliquen A. G. Andreou and R. E. Jenkins "A heteroassociative memory using current-mode MOS analog VLSI circuits," IEEE Trans. Circuits Syst. vol. 36 no. 5 pp. 747-755 May 1989.
-
(1989)
IEEE Trans. Circuits Syst
, vol.36
, Issue.5
, pp. 747-755
-
-
Boahen, K.A.1
Pouliquen, P.O.2
Andreou, A.G.3
Jenkins, R.E.4
-
21
-
-
0033740171
-
Point-to-point connectivity between neuromorphic chips using address events
-
May
-
K. Boahen "Point-to-point connectivity between neuromorphic chips using address events," IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. vol. 47 no. 5 pp. 416-434 May 2000.
-
(2000)
IEEE Trans. Circuits Syst. II Analog Digit. Signal Process
, vol.47
, Issue.5
, pp. 416-434
-
-
Boahen, K.1
-
23
-
-
0025532312
-
A VLSI architecture for high-performance low-cost on-chip learning
-
D. Hammerstrom "A VLSI architecture for high-performance low-cost on-chip learning," in Proc. Int. Joint Conf. Neural Netw. 1990 pp. 537-544.
-
(1990)
Proc. Int. Joint Conf. Neural Netw
, pp. 537-544
-
-
Hammerstrom, D.1
-
24
-
-
0000293092
-
Artificial dendritic trees
-
J. G. Elias "Artificial dendritic trees," Neural Comput. vol. 5 no. 4 pp. 648-664 1993.
-
(1993)
Neural Comput
, vol.5
, Issue.4
, pp. 648-664
-
-
Elias, J.G.1
-
25
-
-
0003005916
-
A pulse-coded communications infrastructure for neuromorphic systems
-
W. Maass and C. M. Bishop Eds. Cambridge MA USA: MIT Press ch. 6
-
S. R. Deiss R. J. Douglas and A. M. Whatley "A pulse-coded communications infrastructure for neuromorphic systems," Pulsed Neural Networks W. Maass and C. M. Bishop Eds. Cambridge MA USA: MIT Press 1999 ch. 6 pp. 157-178.
-
(1999)
Pulsed Neural Networks
, pp. 157-178
-
-
Deiss, S.R.1
Douglas, R.J.2
Whatley, A.M.3
-
26
-
-
33846098196
-
Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses
-
Jan
-
R. Vogelstein U. Mallik J. Vogelstein and G. Cauwenberghs "Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses," IEEE Trans. Neural Netw. vol. 18 no. 1 pp. 253-265 Jan. 2007.
-
(2007)
IEEE Trans. Neural Netw
, vol.18
, Issue.1
, pp. 253-265
-
-
Vogelstein, R.1
Mallik, U.2
Vogelstein, J.3
Cauwenberghs, G.4
-
28
-
-
84856545137
-
An event-driven multi-kernel convolution processor module for event-driven vision sensors
-
Feb
-
L. Camunas-Mesa C. Zamarreno-Ramos A. Linares-Barranco A. J. Acosta-Jimenez T. Serrano-Gotarredona and B. Linares-Barranco "An event-driven multi-kernel convolution processor module for event-driven vision sensors," IEEE J. Solid-State Circuits vol. 47 no. 2 pp. 504-517 Feb. 2012.
-
(2012)
IEEE J. Solid-State Circuits
, vol.47
, Issue.2
, pp. 504-517
-
-
Camunas-Mesa, L.1
Zamarreno-Ramos, C.2
Linares-Barranco, A.3
Acosta-Jimenez, A.J.4
Serrano-Gotarredona, T.5
Linares-Barranco, B.6
-
29
-
-
84897963931
-
An event-based neural network architecture with an asynchronous programmable synaptic memory
-
Feb
-
S. Moradi and G. Indiveri "An event-based neural network architecture with an asynchronous programmable synaptic memory," IEEE Trans. Biomed. Circuits Syst. vol. 8 no. 1 pp. 98-107 Feb. 2014.
-
(2014)
IEEE Trans. Biomed. Circuits Syst
, vol.8
, Issue.1
, pp. 98-107
-
-
Moradi, S.1
Indiveri, G.2
-
30
-
-
33846684161
-
A summating exponentially-decaying CMOS synapse for spiking neural systems
-
Cambridge MA USA: MIT Press
-
R. Z. Shi and T. K. Horiuchi "A summating exponentially-decaying CMOS synapse for spiking neural systems," in Advances in Neural Information Processing Systems (NIPS). Cambridge MA USA: MIT Press 2004.
-
(2004)
Advances in Neural Information Processing Systems (NIPS
-
-
Shi, R.Z.1
Horiuchi, T.K.2
-
31
-
-
36348982825
-
Synchrony in silicon: The gamma rhythm
-
Nov
-
J. V. Arthur and K. A. Boahen "Synchrony in silicon: The gamma rhythm," IEEE Trans. Neural Netw. vol. 18 no. 6 pp. 1815-1825 Nov. 2007.
-
(2007)
IEEE Trans. Neural Netw
, vol.18
, Issue.6
, pp. 1815-1825
-
-
Arthur, J.V.1
Boahen, K.A.2
-
33
-
-
0027841342
-
Log-domain filtering: An approach to current-mode filtering
-
D. R. Frey "Log-domain filtering: An approach to current-mode filtering," Inst. Electr. Eng. Proc. G Circuits Devices Syst. vol. 140 no. 6 pp. 406-416 1993.
-
(1993)
Inst. Electr. Eng. Proc. G Circuits Devices Syst
, vol.140
, Issue.6
, pp. 406-416
-
-
Frey, D.R.1
-
34
-
-
84899010313
-
A recurrent model of orientation maps with simple and complex cells
-
Cambridge MA USA: MIT Press
-
P. Merolla and K. A. Boahen "A recurrent model of orientation maps with simple and complex cells," in Advances in Neural Information Processing Systems (NIPS). Cambridge MA USA: MIT Press 2004 pp. 995-1002.
-
(2004)
Advances in Neural Information Processing Systems (NIPS
, pp. 995-1002
-
-
Merolla, P.1
Boahen, K.A.2
-
37
-
-
0032185581
-
Analog versus digital: Extrapolating from electronics to neurobiology
-
R. Sarpeshkar "Analog versus digital: Extrapolating from electronics to neurobiology," Neural Comput. vol. 10 no. 7 pp. 1601-1638 1998.
-
(1998)
Neural Comput
, vol.10
, Issue.7
, pp. 1601-1638
-
-
Sarpeshkar, R.1
-
39
-
-
84875051127
-
Multicasting mesh AER: A scalable assembly approach for reconfigurable neuromorphic structured AER systems. Application to ConvNets
-
Feb
-
C. Zamarreno-Ramos A. Linares-Barranco T. Serrano-Gotarredona and B. Linares-Barranco "Multicasting mesh AER: A scalable assembly approach for reconfigurable neuromorphic structured AER systems. Application to ConvNets," IEEE Trans. Biomed. Circuits Syst. vol. 7 no. 1 pp. 82-102 Feb. 2012.
-
(2012)
IEEE Trans. Biomed. Circuits Syst
, vol.7
, Issue.1
, pp. 82-102
-
-
Zamarreno-Ramos, C.1
Linares-Barranco, A.2
Serrano-Gotarredona, T.3
Linares-Barranco, B.4
-
41
-
-
84862237704
-
VLSI implementation of a 2.8 Gevent/s packet based AER interface with routing and event sorting functionality
-
DOI: 10.3389/fnins.2011.00117
-
S. Scholze S. Schiefer J. Partzsch S. Hartmann C. Mayr S. Höppner H. Eisenreich S. Henker B. Vogginger and R. Schüffny "VLSI implementation of a 2.8 Gevent/s packet based AER interface with routing and event sorting functionality," Front. Neurosci. vol. 5 no. 117 2011 DOI: 10.3389/fnins.2011.00117.
-
(2011)
Front. Neurosci
, vol.5
, Issue.117
-
-
Scholze, S.1
Schiefer, S.2
Partzsch, J.3
Hartmann, S.4
Mayr, C.5
Höppner, S.6
Eisenreich, H.7
Henker, S.8
Vogginger, B.9
Schüffny, R.10
-
46
-
-
0039101652
-
The tree machine: A highly concurrent computing environment
-
Pasadena CA USA Tech. Rep. Caltech-CS-TR
-
S. Browning "The tree machine: A highly concurrent computing environment," California Inst. Technol. Pasadena CA USA Tech. Rep. Caltech-CS-TR-80-3760 1980.
-
(1980)
California Inst. Technol
, pp. 80-3760
-
-
Browning, S.1
-
47
-
-
0019007733
-
The binary tree as an interconnection network: Applications to multiprocessor systems and VLSI
-
Apr
-
E. Horowitz and A. Zorat "The binary tree as an interconnection network: Applications to multiprocessor systems and VLSI," IEEE Trans. Comput. vol. C-30 no. 4 pp. 247-253 Apr. 1981.
-
(1981)
IEEE Trans. Comput
, vol.C-30
, Issue.4
, pp. 247-253
-
-
Horowitz, E.1
Zorat, A.2
-
48
-
-
79951906654
-
Scalable network-on-chip architecture for configurable neural networks
-
D. Vainbrand and R. Ginosar "Scalable network-on-chip architecture for configurable neural networks," Microprocess. Microsyst. vol. 35 no. 2 pp. 152-166 2011.
-
(2011)
Microprocess. Microsyst
, vol.35
, Issue.2
, pp. 152-166
-
-
Vainbrand, D.1
Ginosar, R.2
-
49
-
-
0022693272
-
Parabolic bursting in an excitable system coupled with a slow oscillation
-
Apr
-
G. B. Ermentrout and N. Kopell "Parabolic bursting in an excitable system coupled with a slow oscillation," SIAM J. Appl. Math. vol. 46 no. 2 pp. 233-253 Apr. 1986.
-
(1986)
SIAM J. Appl. Math
, vol.46
, Issue.2
, pp. 233-253
-
-
Ermentrout, G.B.1
Kopell, N.2
-
50
-
-
0002236344
-
An efficient method for computing synaptic conductances based on a kinetic model of receptor binding
-
Jan
-
A. Destexhe Z. F. Mainen and T. J. Sejnowski "An efficient method for computing synaptic conductances based on a kinetic model of receptor binding," Neural Comput. vol. 6 no. 1 pp. 14-18 Jan. 1994.
-
(1994)
Neural Comput
, vol.6
, Issue.1
, pp. 14-18
-
-
Destexhe, A.1
Mainen, Z.F.2
Sejnowski, T.J.3
-
51
-
-
84900478290
-
The hexagonal resistive network and the circular approximation
-
Pasadena CA USA Tech. Rep. CaltechCSTR: 1988.cs-tr-88-07
-
D. I. Feinstein "The hexagonal resistive network and the circular approximation," California Inst. Technol. Pasadena CA USA Tech. Rep. CaltechCSTR:1988.cs-tr-88-07 1988.
-
(1988)
California Inst. Technol
-
-
Feinstein, D.I.1
-
52
-
-
0017503796
-
CMOS analog integrated circuits based on weak inversion operation
-
Jun
-
E. Vittoz and J. Fellrath "CMOS analog integrated circuits based on weak inversion operation," IEEE J. Solid-State Circuits vol. 12 no. 3 pp. 224-231 Jun. 1977.
-
(1977)
IEEE J. Solid-State Circuits
, vol.12
, Issue.3
, pp. 224-231
-
-
Vittoz, E.1
Fellrath, J.2
-
53
-
-
21244466365
-
Bias current generators with wide dynamic range
-
Jun
-
T. Delbrück and A. V. Schaik "Bias current generators with wide dynamic range," Analog Integr. Circuits Signal Process. vol. 43 no. 3 pp. 247-268 Jun. 2005.
-
(2005)
Analog Integr. Circuits Signal Process
, vol.43
, Issue.3
, pp. 247-268
-
-
Delbrück, T.1
Schaik, A.V.2
-
54
-
-
84867330171
-
Dynamical system guided mapping of quantitative neuronal models onto neuromorphic hardware
-
Oct
-
P. Gao B. V. Benjamin and K. Boahen "Dynamical system guided mapping of quantitative neuronal models onto neuromorphic hardware," IEEE Trans. Circuits Syst. I Reg. Papers vol. 59 no. 10 pp. 2383-2394 Oct. 2012.
-
(2012)
IEEE Trans. Circuits Syst. i Reg. Papers
, vol.59
, Issue.10
, pp. 2383-2394
-
-
Gao, P.1
Benjamin, B.V.2
Boahen, K.3
-
55
-
-
79955521201
-
Silicon-neuron design: A dynamical systems approach
-
May
-
J. V. Arthur and K. Boahen "Silicon-neuron design: A dynamical systems approach," IEEE Trans. Circuits Syst. I Reg. Papers vol. 58 no. 5 pp. 1034-1043 May 2011.
-
(2011)
IEEE Trans. Circuits Syst. i Reg. Papers
, vol.58
, Issue.5
, pp. 1034-1043
-
-
Arthur, J.V.1
Boahen, K.2
-
56
-
-
33847289683
-
Thermodynamically equivalent silicon models of voltage-dependent ion channels
-
K. M. Hynna and K. Boahen "Thermodynamically equivalent silicon models of voltage-dependent ion channels," Neural Comput. vol. 19 no. 2 pp. 327-350 2007.
-
(2007)
Neural Comput
, vol.19
, Issue.2
, pp. 327-350
-
-
Hynna, K.M.1
Boahen, K.2
-
57
-
-
13144278342
-
An on-off log domain circuit that recreates adaptive filtering in the retina
-
Jan
-
K. A. Zaghloul and K. A. Boahen "An on-off log domain circuit that recreates adaptive filtering in the retina," IEEE Trans. Circuits Syst. I Reg. Papers vol. 52 no. 1 pp. 99-107 Jan. 2005.
-
(2005)
IEEE Trans. Circuits Syst. i Reg. Papers
, vol.52
, Issue.1
, pp. 99-107
-
-
Zaghloul, K.A.1
Boahen, K.A.2
-
60
-
-
0002927123
-
Programming in VLSI: From communicating processes to delay-insensitive circuits
-
Reading MA USA: Addison-Wesley
-
A. Martin "Programming in VLSI: From communicating processes to delay-insensitive circuits," in Developments in Concurrency and Communication. Reading MA USA: Addison-Wesley 1991 pp. 1-64.
-
(1991)
Developments in Concurrency and Communication
, pp. 1-64
-
-
Martin, A.1
-
61
-
-
33947432403
-
Asynchronous techniques for system-on-chip design
-
Jun
-
A. Martin and M. Nystrom "Asynchronous techniques for system-on-chip design," Proc. IEEE vol. 94 no. 6 pp. 1089-1120 Jun. 2006.
-
(2006)
Proc. IEEE
, vol.94
, Issue.6
, pp. 1089-1120
-
-
Martin, A.1
Nystrom, M.2
-
62
-
-
4043137376
-
A burst-mode word-serial address-event link I: Transmitter design
-
Jul
-
K. A. Boahen "A burst-mode word-serial address-event link I: Transmitter design," IEEE Trans. Circuits Syst. I Reg. Papers vol. 51 no. 7 pp. 1269-1280 Jul. 2004.
-
(2004)
IEEE Trans. Circuits Syst. i Reg. Papers
, vol.51
, Issue.7
, pp. 1269-1280
-
-
Boahen, K.A.1
-
63
-
-
4043086402
-
A burst-mode word-serial address-event link II: Receiver design
-
Jul
-
K. A. Boahen "A burst-mode word-serial address-event link II: Receiver design," IEEE Trans. Circuits Syst. I Reg. Papers vol. 51 no. 7 pp. 1281-1291 Jul. 2004.
-
(2004)
IEEE Trans. Circuits Syst. i Reg. Papers
, vol.51
, Issue.7
, pp. 1281-1291
-
-
Boahen, K.A.1
-
64
-
-
4043065121
-
A burst-mode word-serial address-event link III: Analysis and test results
-
Jul
-
K. A. Boahen "A burst-mode word-serial address-event link III: Analysis and test results," IEEE Trans. Circuits Syst. I Reg. Papers vol. 51 no. 7 pp. 1292-1300 Jul. 2004.
-
(2004)
IEEE Trans. Circuits Syst. i Reg. Papers
, vol.51
, Issue.7
, pp. 1292-1300
-
-
Boahen, K.A.1
-
65
-
-
0026236673
-
Scanners for visualizing activity of analog VLSI circuitry
-
C. Mead and T. Delbruck "Scanners for visualizing activity of analog VLSI circuitry," Analog Integr. Circuits Signal Process. vol. 1 no. 2 pp. 93-106 1991.
-
(1991)
Analog Integr. Circuits Signal Process
, vol.1
, Issue.2
, pp. 93-106
-
-
Mead, C.1
Delbruck, T.2
-
69
-
-
84867681939
-
Silicon neurons that compute
-
S. Choudhary S. Sloan S. Fok A. Neckar E. Trautmann P. Gao T. Stewart C. Eliasmith and K. Boahen "Silicon neurons that compute," in Proc. Int. Conf. Artif. Neural Netw. 2012 pp. 121-128.
-
(2012)
Proc. Int. Conf. Artif. Neural Netw
, pp. 121-128
-
-
Choudhary, S.1
Sloan, S.2
Fok, S.3
Neckar, A.4
Trautmann, E.5
Gao, P.6
Stewart, T.7
Eliasmith, C.8
Boahen, K.9
-
73
-
-
84875055083
-
A learning-enabled neuron array IC based upon transistor channel models of biological phenomena
-
Feb
-
S. Brink S. Nease P. Hasler S. Ramakrishnan R. Wunderlich A. Basu and B. Degnan "A learning-enabled neuron array IC based upon transistor channel models of biological phenomena," IEEE Trans. Biomed. Circuits Syst. vol. 7 no. 1 pp. 71-81 Feb. 2013.
-
(2013)
IEEE Trans. Biomed. Circuits Syst
, vol.7
, Issue.1
, pp. 71-81
-
-
Brink, S.1
Nease, S.2
Hasler, P.3
Ramakrishnan, S.4
Wunderlich, R.5
Basu, A.6
Degnan, B.7
-
74
-
-
0034762808
-
Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons
-
D. H. Goldberg G. Cauwenberghs and A. G. Andreou "Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons," Neural Netw. vol. 14 no. 6 pp. 781-793 2001.
-
(2001)
Neural Netw
, vol.14
, Issue.6
, pp. 781-793
-
-
Goldberg, D.H.1
Cauwenberghs, G.2
Andreou, A.G.3
-
76
-
-
77951026760
-
Nanoscale memristor device as synapse in neuromorphic systems
-
S. H. Jo T. Chang I. Ebong B. B. Bhadviya P. Mazumder and W. Lu "Nanoscale memristor device as synapse in neuromorphic systems," Nano Lett. vol. 10 no. 4 pp. 1297-1301 2010.
-
(2010)
Nano Lett
, vol.10
, Issue.4
, pp. 1297-1301
-
-
Jo, S.H.1
Chang, T.2
Ebong, I.3
Bhadviya, B.B.4
Mazumder, P.5
Lu, W.6
|