Design of silicon brains in the nano-CMOS era: Spiking neurons, learning synapses and neural architecture optimization

Neural Networks

Volumn 45, Issue , 2013, Pages 4-26

  Cassidy, Andrew S ^a   Georgiou, Julius ^b   Andreou, Andreas G ^a,b  

^a Johns Hopkins University   (United States)

^b UNIVERSITY OF CYPRUS   (Cyprus)

Author keywords

FPGA neural arrays; Learning in silicon; Neuromorphic engineering; Silicon brains; Silicon neurons

Indexed keywords

ARITHMETIC LOGIC UNIT; COMMUNICATION PROCESSORS; COMPUTATIONAL STRUCTURE; DESIGN METHODOLOGY; NEURAL ARCHITECTURES; NEUROMORPHIC ARCHITECTURES; NEUROMORPHIC ENGINEERING; SILICON NEURON;

DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NEURAL NETWORKS; OPTIMIZATION; SILICON;

NEURONS;

SILICON;

ALGORITHM; ARTICLE; ARTIFICIAL NEURAL NETWORK; ARTIFICIAL NEURON; CYTOARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAY; LEAKY INTEGRATE AND FIRE NEURON MODEL; MACHINE LEARNING; MATHEMATICAL MODEL; NERVE CELL PLASTICITY; NEUROMORPHIC ENGINEERING; PRIORITY JOURNAL; PROCESS OPTIMIZATION; SEMICONDUCTOR; SILICON BRAIN; SPIKE TIMING DEPENDENT PLASTICITY; SYNAPSE; VALIDITY;

FPGA NEURAL ARRAYS; LEARNING IN SILICON; NEUROMORPHIC ENGINEERING; SILICON BRAINS; SILICON NEURONS;

ACTION POTENTIALS; BRAIN; COMPUTER SIMULATION; HUMANS; LEARNING; MODELS, NEUROLOGICAL; NEURONS;

EID: 84880823556     PISSN: 08936080     EISSN: 18792782     Source Type: Journal    
DOI: 10.1016/j.neunet.2013.05.011     Document Type: Article

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