Dynamically reconfigurable silicon array of spiking neurons with conductance-based synapses

IEEE Transactions on Neural Networks

Volumn 18, Issue 1, 2007, Pages 253-265

  Vogelstein, R Jacob ^a   Mallik, Udayan ^b,c   Vogelstein, Joshua T ^d   Cauwenberghs, Gert ^e  

^a Johns Hopkins University   (United States)

^b Johns Hopkins University   (United States)

^c NASA GODDARD SPACE FLIGHT CENTER   (United States)

^d JOHNS HOPKINS UNIVERSITY   (United States)

^e UNIVERSITY OF CALIFORNIA SAN DIEGO   (United States)

Author keywords

Address event representation (AER); Dynamically reconfigurable network; Membrane conductance; Mixed signal very large scale integration (VLSI); Neural emulator; Neurotransmitter quantal release; Switched capacitor

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC CONDUCTANCE; MICROPROCESSOR CHIPS; VLSI CIRCUITS;

DYNAMICALLY RECONFIGURABLE NETWORK; MEMBRANE CONDUCTANCE; MIXED-SIGNAL VERY LARGE SCALE INTEGRATION (VLSI); NEURAL EMULATOR; NEUROTRANSMITTER QUANTAL RELEASE; SPIKING NEURAL NETWORKS; SWITCHED CAPACITOR;

NEURAL NETWORKS;

SILICON;

ACTION POTENTIAL; ARTICLE; ARTIFICIAL NEURAL NETWORK; BIOLOGICAL MODEL; BIOMIMETICS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY; ELECTRONICS; EQUIPMENT; EQUIPMENT DESIGN; EVALUATION; INSTRUMENTATION; METHODOLOGY; NERVE CELL; NERVE CELL NETWORK; PHYSIOLOGY; SYNAPTIC TRANSMISSION;

ACTION POTENTIALS; BIOMIMETICS; COMPUTER SIMULATION; COMPUTER-AIDED DESIGN; ELECTRIC CONDUCTIVITY; ELECTRONICS; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; MODELS, NEUROLOGICAL; NERVE NET; NEURAL NETWORKS (COMPUTER); NEURONS; SILICON; SYNAPTIC TRANSMISSION;

EID: 33846098196     PISSN: 10459227     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNN.2006.883007     Document Type: Article

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