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Volumn , Issue , 2010, Pages

Scalable event routing in hierarchical neural array architecture with global synaptic connectivity

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; ECONOMIC AND SOCIAL EFFECTS; NANOTECHNOLOGY;

EID: 77952363834     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/cnna.2010.5430296     Document Type: Conference Paper
Times cited : (27)

References (15)
  • 2
    • 33748512220 scopus 로고    scopus 로고
    • A throughput-on-demand address-event transmitter for neuromorphic chips
    • K. Boahen, "A throughput-on-demand address-event transmitter for neuromorphic chips, " in ARVLSI, 1999, pp. 72-87.
    • (1999) ARVLSI , pp. 72-87
    • Boahen, K.1
  • 5
    • 0003005916 scopus 로고    scopus 로고
    • A pulse-coded communications infrastructure for neuromorphic systems
    • MIT Press, (Mass W. Bishop, C.M. ed)
    • S. Deiss, R. Douglas, and A. Whatley, "A pulse-coded communications infrastructure for neuromorphic systems, " Pulsed Neural Networks, MIT Press, (Mass W., Bishop, C.M., ed), 1999.
    • (1999) Pulsed Neural Networks
    • Deiss, S.1    Douglas, R.2    Whatley, A.3
  • 8
    • 33846098196 scopus 로고    scopus 로고
    • Dynamically reconfigurable silicon array of spiking neurons with conductance based synapses
    • Jan.
    • R. Vogelstein, U. Mallik, J. Vogelstein, and G. Cauwenberghs, "Dynamically reconfigurable silicon array of spiking neurons with conductancebased synapses, " Neural Networks, IEEE Transactions on, vol. 18, no. 1, pp. 253-265, Jan. 2007.
    • (2007) Neural Networks, IEEE Transactions on , vol.18 , Issue.1 , pp. 253-265
    • Vogelstein, R.1    Mallik, U.2    Vogelstein, J.3    Cauwenberghs, G.4
  • 11
    • 84864066905 scopus 로고    scopus 로고
    • Learning in silicon: Timing is everything
    • J. V. Arthur and K. Boahen, "Learning in silicon: Timing is everything, " in NIPS, 2005.
    • (2005) NIPS
    • Arthur, J.V.1    Boahen, K.2
  • 13
    • 0022141776 scopus 로고
    • Fat-trees: Universal networks for hardware-efficient supercomputing
    • C. E. Leiserson, "Fat-trees: universal networks for hardware-efficient supercomputing, " IEEE Trans. Comput., vol. 34, no. 10, pp. 892-901, 1985.
    • (1985) IEEE Trans. Comput. , vol.34 , Issue.10 , pp. 892-901
    • Leiserson, C.E.1
  • 14
    • 0000861722 scopus 로고
    • A proof for the queuing formula: 1 = λω
    • J. D. C. Little, "A proof for the queuing formula: 1 = λω, " Operations Research, vol. 9, no. 3, pp. 383-387, 1961.
    • (1961) Operations Research , vol.9 , Issue.3 , pp. 383-387
    • Little, J.D.C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.