-
2
-
-
33748512220
-
A throughput-on-demand address-event transmitter for neuromorphic chips
-
K. Boahen, "A throughput-on-demand address-event transmitter for neuromorphic chips, " in ARVLSI, 1999, pp. 72-87.
-
(1999)
ARVLSI
, pp. 72-87
-
-
Boahen, K.1
-
3
-
-
0035011627
-
High dynamic range, arbitrated address event representation digital imager
-
E. Culurciello, R. Etienne-Cummings, and K. Boahen, "High dynamic range, arbitrated address event representation digital imager, " in ISCAS (3), 2001, pp. 505-508. (Pubitemid 32469902)
-
(2001)
Proceedings - IEEE International Symposium on Circuits and Systems
, vol.3
, pp. 505-508
-
-
Culurciello, E.1
Etienne-Cummings, R.2
Boahen, K.3
-
4
-
-
0028744834
-
Connectionism without the connections
-
Jun-2 Jul, vol.2
-
S. Deiss, "Connectionism without the connections, " in Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on, vol. 2, Jun-2 Jul 1994, pp. 1217-1221 vol.2.
-
(1994)
Neural Networks, 1994. IEEE World Congress on Computational Intelligence., 1994 IEEE International Conference on
, vol.2
, pp. 1217-1221
-
-
Deiss, S.1
-
5
-
-
0003005916
-
A pulse-coded communications infrastructure for neuromorphic systems
-
MIT Press, (Mass W. Bishop, C.M. ed)
-
S. Deiss, R. Douglas, and A. Whatley, "A pulse-coded communications infrastructure for neuromorphic systems, " Pulsed Neural Networks, MIT Press, (Mass W., Bishop, C.M., ed), 1999.
-
(1999)
Pulsed Neural Networks
-
-
Deiss, S.1
Douglas, R.2
Whatley, A.3
-
6
-
-
56349083817
-
Spinnaker: Mapping neural networks onto a massively-parallel chip multiprocessor
-
June
-
M. Khan, D. Lester, L. Plana, A. Rast, X. Jin, E. Painkras, and S. Furber, "Spinnaker: Mapping neural networks onto a massively-parallel chip multiprocessor, " in Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence). IEEE International Joint Conference on, June 2008, pp. 2849-2856.
-
(2008)
Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence). IEEE International Joint Conference on
, pp. 2849-2856
-
-
Khan, M.1
Lester, D.2
Plana, L.3
Rast, A.4
Jin, X.5
Painkras, E.6
Furber, S.7
-
7
-
-
56349143763
-
Realizing biological spiking network models in a configurable wafer-scale hardware system
-
June
-
J. Fieres, J. Schemmel, and K. Meier, "Realizing biological spiking network models in a configurable wafer-scale hardware system, " in Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence). IEEE International Joint Conference on, June 2008, pp. 969-976.
-
(2008)
Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence). IEEE International Joint Conference on
, pp. 969-976
-
-
Fieres, J.1
Schemmel, J.2
Meier, K.3
-
8
-
-
33846098196
-
Dynamically reconfigurable silicon array of spiking neurons with conductance based synapses
-
Jan.
-
R. Vogelstein, U. Mallik, J. Vogelstein, and G. Cauwenberghs, "Dynamically reconfigurable silicon array of spiking neurons with conductancebased synapses, " Neural Networks, IEEE Transactions on, vol. 18, no. 1, pp. 253-265, Jan. 2007.
-
(2007)
Neural Networks, IEEE Transactions on
, vol.18
, Issue.1
, pp. 253-265
-
-
Vogelstein, R.1
Mallik, U.2
Vogelstein, J.3
Cauwenberghs, G.4
-
9
-
-
70349253937
-
-
R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gomez-Rodriguez, K. Camunas-Mesa, R. Berner, M. Rivas-Perez, T. Delbruck, S. Liu, R. Douglas, P. Hafliger, G. Jimenez- Moreno, A. Ballcels, T. Serrano-Gotarredona, A. Acosta-Jimenez, and B. Linares-Barranco, "CAVIAR: A 45k neuron, 5M synapse, 12G connects/s AER hardware sensory-processing-learning-actuating system for high-speed visual object recognition and tracking, " vol. 20, no. 9, 2009, pp. 1417-1438.
-
(2009)
CAVIAR: A 45k Neuron, 5M Synapse, 12G Connects/s AER Hardware Sensory-processing-learning-actuating System for High-speed Visual Object Recognition and Tracking
, vol.20
, Issue.9
, pp. 1417-1438
-
-
Serrano-Gotarredona, R.1
Oster, M.2
Lichtsteiner, P.3
Linares-Barranco, A.4
Paz-Vicente, R.5
Gomez-Rodriguez, F.6
Camunas-Mesa, K.7
Berner, R.8
Rivas-Perez, M.9
Delbruck, T.10
Liu, S.11
Douglas, R.12
Hafliger, P.13
Moreno G.J.-14
Ballcels, A.15
Serrano-Gotarredona, T.16
Acosta-Jimenez, A.17
Linares-Barranco, B.18
-
10
-
-
84900514794
-
Spike timing-dependent plasticity in the address domain
-
R. J. Vogelstein, F. Tenore, R. Philipp, M. S. Adlerstein, D. H. Goldberg, and G. Cauwenberghs, "Spike timing-dependent plasticity in the address domain, " in NIPS, 2002, pp. 1147-1154.
-
(2002)
NIPS
, pp. 1147-1154
-
-
Vogelstein, R.J.1
Tenore, F.2
Philipp, R.3
Adlerstein, M.S.4
Goldberg, D.H.5
Cauwenberghs, G.6
-
11
-
-
84864066905
-
Learning in silicon: Timing is everything
-
J. V. Arthur and K. Boahen, "Learning in silicon: Timing is everything, " in NIPS, 2005.
-
(2005)
NIPS
-
-
Arthur, J.V.1
Boahen, K.2
-
12
-
-
33947393626
-
Expandable networks for neuromorphic chips
-
Feb.
-
P. A. Merolla, J. V. Arthur, B. E. Shi, and K. A. Boahen, "Expandable networks for neuromorphic chips, " Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 54, no. 2, pp. 301-311, Feb. 2007.
-
(2007)
Circuits and Systems I: Regular Papers, IEEE Transactions on
, vol.54
, Issue.2
, pp. 301-311
-
-
Merolla, P.A.1
Arthur, J.V.2
Shi, B.E.3
Boahen, K.A.4
-
13
-
-
0022141776
-
Fat-trees: Universal networks for hardware-efficient supercomputing
-
C. E. Leiserson, "Fat-trees: universal networks for hardware-efficient supercomputing, " IEEE Trans. Comput., vol. 34, no. 10, pp. 892-901, 1985.
-
(1985)
IEEE Trans. Comput.
, vol.34
, Issue.10
, pp. 892-901
-
-
Leiserson, C.E.1
-
14
-
-
0000861722
-
A proof for the queuing formula: 1 = λω
-
J. D. C. Little, "A proof for the queuing formula: 1 = λω, " Operations Research, vol. 9, no. 3, pp. 383-387, 1961.
-
(1961)
Operations Research
, vol.9
, Issue.3
, pp. 383-387
-
-
Little, J.D.C.1
-
15
-
-
0003944096
-
-
New York, NY, USA: John Wiley & Sons, Inc.
-
E. Gelenbe and G. Pujolle, Introduction to queueing networks. New York, NY, USA: John Wiley & Sons, Inc., 1987.
-
(1987)
Introduction to Queueing Networks
-
-
Gelenbe, E.1
Pujolle, G.2
|