A Delay-insensitive address-event link

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2009, Pages 55-62

  Lin, Joseph ^a   Boahen, Kwabena ^b  

^a Johns Hopkins University   (United States)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITIONAL COLUMNS; BUNDLED DATA; DELAY PENALTY; DELAY-INSENSITIVE IMPLEMENTATIONS; INPUT PORT; OFF-CHIP; ON CHIPS; POINT-TO-POINT CHANNELS; TWO-DIMENSIONAL ARRAYS; VIRTUAL POINTS;

EID: 70349271003     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: 10.1109/ASYNC.2009.25     Document Type: Conference Paper

References (15)

1. J. Lin, P. Merolla, J. Arthur, and K. Boahen, "Programmable connections in neuromorphic grids, " Circuits and Systems, 2006. MWSCAS '06. 49th IEEE International Midwest Symposium on, vol.1, pp. 80-84, Aug. 2006.
2. P. Merolla, J. Arthur, B. E. Shi, and K. Boahen, "Expandable networks for neuromorphic chips, " IEEE Trans. Circuits Syst. I, vol.54, no.2, pp. 301-311, 2007.
3. L. Plana, S. Furber, S. Temple, M. Khan, Y. Shi, J. Wu, and S. Yang, "A gals infrastructure for a massively parallel multiprocessor, " Design and Test of Computers, IEEE, vol.24, no.5, pp. 454-463, Sept.-Oct. 2007.
4. M. Sivilotti, "Wiring considerations in analog VLSI systems, with application to field-programmable networks, " Ph.D. dissertation, California Institute of Technology, Pasadena CA, 1991.
5. M. Mahowald, An Analog VLSI Stereoscopic Vision System. Boston, MA: Kluwer Academic Pub., 1994.
6. K. Boahen, "A burst-mode word-serial address-event link-i: transmitter design, " IEEE Trans. Circuits Syst. I, vol.51, no.7, pp. 1269-1280, 2004.
7. "A burst-mode word-serial address-event link-ii: receiver design, " IEEE Trans. Circuits Syst. I, vol.51, no.7, pp. 1281-1291, 2004.
8. K. Zaghloul and K. A. Boahen, "Optic nerve signals in a neuromorphic chip: Outer and inner retina models, " IEEE Trans. on Biomed. Eng., vol.51, no.4, pp. 657-666, Submitted.
9. T. Y. W. Choi, B. E. Shi, and K. Boahen, "An on-off orientation selective address event representation image transceiver chip, " IEEE Trans. Circuits Syst. I, vol.51, no.2, pp. 342-353, 2004.
10. P. Merolla and K. Boahen, "A recurrent model of orientation maps with simple and complex cells, " in Advances in Neural Information Processing, S. Thrun and L. Saul, Eds., vol.15. San Mateo CA: Morgan Kaufman, 2004, pp. 995-1002.
11. T. Y. W. Choi, P. Merolla, J. Arthur, B. E. Shi, and K. Boahen, "Neuromorphic implementation of orientation hypercolumns, " IEEE Trans. Circuits Syst. I, vol.52, no.6, pp. 1049-1060, 2005.
12. J. Arthur and K. Boahen, "Synchrony in silicon: The gamma rhythm, " IEEE Trans. Neural Networks, vol.18, no.6, pp. 1815-1825, 2007.
13. C. A. Mead, Introduction to VLSI Systems. Reading MA: Addison Wesley, 1980.
14. A. J. Martin, "Programming in vlsi: From communicating processes to delay-insensitive circuits, " California Institute of Technology, Technical Report CaltechCSTR:1989.cs-tr-89-101, 1989.
15. "Synthesis of asynchronous vlsi circuits, " in Formal Methods For VLSI Design, J. Staunstrup, Ed. North-Holland, 1990, pp. 237-283.