A burst-mode word-serial address-event link - II: Receiver design

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 7, 2004, Pages 1281-1291

  Boahen, Kwabena A ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTER PROGRAMMING; DECODING; DEMULTIPLEXING; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUIT LAYOUT; MULTIPLEXING; PARALLEL PROCESSING SYSTEMS; SIGNAL RECEIVERS; TELECOMMUNICATION LINKS;

ASYNCHRONOUS LOGIC SYNTHESIS; COMMUNICATION CAPACITY; EVENT DRIVEN COMMUNICATION; NEUROMORPHIC SYSTEMS; PIXEL LEVEL QUANTIZATION; RECEIVER DESIGN;

DIGITAL INTEGRATED CIRCUITS;

EID: 4043086402     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.830702     Document Type: Article

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