A 1-change-in-4 delay-insensitive interchip link

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 3216-3219

  Chandrasekaran, Anand ^a   Boahen, Kwabena ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS PROCESSS; CODE-WORDS; CODEWORD; DATA-RATE; ENCODING AND DECODING; INTER-CHIP; INTERCHIP COMMUNICATIONS; LEVEL-ENCODED DUAL-RAIL; TRANSITION SIGNALING;

CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; FABRICS;

ENCODING (SYMBOLS);

EID: 77955999805     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537933     Document Type: Conference Paper

References (5)

1. A. Chandrasekaran, F. Folowosele, S. Liu, and K. Boahen, "One-changein-four encoders and decoders," in 2007 Telluride Neuromorphic Engineering Workshop Report. Institute for Neuromorphic Engineering, 2007, pp. 37-47, http://ine-web.org/workshops/past-workshops.
2. M. E. Dean, T. E. Williams, and D. L. Dill, "Efficient self-timing with level-encoded 2-phase dual-rail," in Proc. of the 1991 UC Santa Cruz Conference on Advanced Research in VLSI, C. H. Sequin, Ed. Cambridge MA: MIT Press, 1991, pp. 55-70.
3. P. B. McGee, M. Y. Agyekum, M. A. Mohamed, and S. M. Nowick, "A level-encoding transition signaling protocol for high-throughput asynchronous global communication," in 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008, pp. 116-127.
4. A. Martin, Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits, ser. UT Year of Programming Series. Addison-Wesley, 1990, pp. 1-64, http://resolver.caltech.edu/CaltechCSTR:1989.cs-tr-89-01.
5. M. Singh and S. M. Nowick, "Mousetrap: High-speed transition-signaling asynchronous pipelines," IEEE Trans. VLSI, vol. 15(6), pp. 684-698, 2007.