A burst-mode word-serial address-event link - III: Analysis and test results

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 7, 2004, Pages 1292-1300

  Boahen, Kwabena A ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; QUEUEING NETWORKS; TELECOMMUNICATION LINKS; TRANSCEIVERS;

ASYNCHRONOUS LOGIC SYNTHESIS; EVENT DRIVEN COMMUNICATION; FAIR ARBITER DESIGN; MULTIPLE ACCESS INTERCHIP LINK; NEUROMORPHIC SYSTEMS; PARALLEL READOUT; PIXEL LEVEL QUANTIZATION; TIMING ERROR; TWO LEVEL QUEUING MODEL;

DIGITAL INTEGRATED CIRCUITS;

EID: 4043065121     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.830701     Document Type: Article

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