A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2011, Pages

  Merolla, Paul ^a   Arthur, John ^a   Akopyan, Filipp ^a,b   Imam, Nabil ^b   Manohar, Rajit ^b   Modha, Dharmendra S ^a  

^a IBM ALMADEN RESEARCH CENTER   (United States)

^b Department of Obstetrics Gynecology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE POWER; BUILDING BLOCKES; CMOS SCALING; COMPACT SIZE; CONFIGURABLE; CROSS-BAR MEMORIES; DIGIT RECOGNITION; DIGITAL IMPLEMENTATION; FAN-OUT; GRAND CHALLENGE; HARDWARE AND SOFTWARE; HUMAN BRAIN; INTEGRATE-AND-FIRE NEURONS; NEUMANN ARCHITECTURE; NEUROMORPHIC; NEURON PARAMETERS; OFFLINE; POST-SILICON; REAL-TIME APPLICATION; RESTRICTED BOLTZMANN MACHINE; ULTRA-LOW POWER CONSUMPTION;

DIGITAL INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LOW POWER ELECTRONICS; STATIC RANDOM ACCESS STORAGE;

MEMORY ARCHITECTURE;

EID: 80455149790     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2011.6055294     Document Type: Conference Paper

References (6)

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