Translinear circuits in subthreshold MOS

Analog Integrated Circuits and Signal Processing

Volumn 9, Issue 2, 1996, Pages 141-166

  Andreou, Andreas G ^a,c   Boahen, Kwabena A ^b,c,d  

^a Johns Hopkins University   (United States)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^c IEEE ^*

^d JOHNS HOPKINS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; GAIN CONTROL; GATES (TRANSISTOR); LINEAR INTEGRATED CIRCUITS; MOSFET DEVICES; VLSI CIRCUITS;

SUBTHRESHOLD MOS; TRANSLINEAR CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030102060     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00166411     Document Type: Article

References (49)

1. B. Gilbert, "Translinear circuits: A proposed classification." Electronics Letters, 11(1), pp. 14-16, 1975; errata, 11(6), p. 136.
2. E. Seevinck, "Analysis and synthesis of translinear integrated circuits." Studies in Electrical and Electronic Engineering, vol. 31. Elsevier: Amsterdam, 1988.
3. B. Gilbert, "Current-mode circuits from a translinear viewpoint: a tutorial." In Chapter 2 of C. Toumazou, F. J. Lidgey and D. G. Haigh, eds., Analogue IC Design: The Current-Mode Approach, IEEE Circuits and Systems Series, vol. 2. Peter Peregrinus Ltd: London, 1990.
4. E. Seevinck and R. J. Wiegerink, "Generalized translinear circuit principle." IEEE Journ. of Solid-State Circuits, SC-26(8), pp. 1198-1102, August 1991.
5. E. A. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operation." IEEE Journ. of Solid-State Circuits, SC-12(3), pp. 224-231, June 1977.
6. E. A. Vittoz, "Micropower techniques." In Y. P. Tsividis and P. Antognetti, eds., VLSI Circuits for Telecommunications. Prentice Hall: 1985.
7. C. A. Mead, Analog VLSI and Neural Systems. Addison-Wesley: Reading, MA, 1989.
8. C. A. Mead, "Neuromorphic electronic systems." Proceedings IEEE, 78(10), pp. 1629-1636, Oct. 1990.
9. A. G. Andreou, "Low power analog VLSI systems for sensory information processing," in B. Sheu, Edgar Sanchez-Sinencio and M. Ismail, eds., Microsystems Technologies for Multimedia Applications: An Introduction. IEEE Press: Los Alamitos, CA, 1995.
10. K. A. Boahen, "Retinomorphic vision systems." Proceedings of MicroNeuro-96. IEEE Computer Society Press: Los Alamitos, CA, 1996.
11. A. G. Andreou and K. A. Boahen, "Synthetic neural circuits using current domain-signal representations." Neural Computation, 1, pp. 489-501, 1989.
12. A. G. Andreou, "Synthetic neural systems using current-mode circuits." Proceedings of the IEEE 1990 International Symposium on Circuits and Systems, New Orleans, pp. 2428-2432, May 1990.
13. A. G. Andreou, K. A. Boahen, P. O. Pouliquen, A. Pavasović, R. E. Jenkins, and K. Strohbehn, "Current-mode subthreshold MOS circuits for analog VLSI neural systems." IEEE Trans. on Neural Networks, 2(2), pp. 205-213, March 1991.
14. M. Cohen and A. G. Andreou, "Current-mode subthreshold MOS implementation of the Herault-Jutten autoadaptive network." IEEE Journ. of Solid-State Circuits, 27(5), pp. 714-727, May 1992.
15. K. A. Boahen and A. G. Andreou, "A contrast sensitive silicon retina with reciprocal synapses." In J. E. Moody, S. J. Hanson, and R. P. Lippmann, eds., Advances in Neural Information Processing Systems 4. Morgan Kaufmann Publishers: San Mateo, CA, 1992.
16. A. G. Andreou and K. A. Boahen, "Neural information processing (II)." In Chapter 8 of Analog VLSI Signal and Information Processing, M. Ismail and T. Fiez, eds. McGraw-Hill: 1994.
17. A. G. Andreou and K. A. Boahen, "A 48,000 pixel, 590,000 transistor silicon retina in current-mode subthreshold CMOS." Proceedings of the 37th Midwest Symposium on Circuits and Systems, pp. 97-102, Lafayette, Louisiana, August 1994.
18. A. G. Andreou and K. A. Boahen, "A 590,000 transistor, 48,000 pixel contrast sensitive, edge enhancing CMOS imager-silicon retina." Proceedings of the 16th Conference on Advanced Research in VLSI, pp. 225-240, Chapel Hill, North Carolina, March 1995.
19. K. Yang and A. G. Andreou, "A multiple input differential amplifier based on charge sharing on a floating gate MOSFET." Journal of Analog Integrated Circuits and Signal Processing, 6, pp. 197-208, November 1994.
20. B. A. Minch, C. Diorio, P. Hasler, and C. A. Mead, "Translinear circuits using subthreshold floating-gate MOS transistors." Journal of Analog Integrated Circuits and Signal Processing, this issue.
21. A. Fabre, "Dual translinear voltage/current convertor." Electronics Letters, 19(24), pp. 1030-1031, 1983.
22. A. Fabre, "Wideband translinear current convertor." Electronics Letters, 20, pp. 241-242, 1984.
23. P. M. Furth and A. G. Andreou, "A high-drive low-power BiC-MOS buffer using compound PMOS/NPN transistors." Proceedings of the 36th Midwest Symposium on Circuits and Systems, pp. 1369-1372, Detroit, Michigan, August 1993.
24. A. G. Andreou, K. Strohbehn, and R. Jenkins, "A silicon retina for motion computation." Proceedings of the IEEE 1991 International Symposium on Circuits and Systems, Singapore, pp. 1373-1376, June 1991.
25. Z. Kalayjian, A. G Andreou, L. Wolff, and J. Williams, "Integrated 1-D polarization imagers." Proceedings of the 29th Annual Conference on Information Sciences and Systems, Baltimore, MD, March 1995.
26. X. Arreguit, E. A. Vittoz, F. A. van Schaik, and A. Mortara, "Analog implementation of low-level vision systems." Proceedings of European Conference on Circuit Theory and Design, pp. 275-280. Elsevier Publishing: September 1993.
27. T. Delbrück, "'Bump' circuits for computing similarity and dissimilarity of analog voltages." Proc. Int. Joint Conf. on Neural Networks, Seattle WA, pp. 475-479, 1991.
28. M. Cohen and A. G. Andreou, "MOS circuit for nonlinear Hebbian learning." Electronics Letters, 28(9), pp. 809-810, April 1992.
29. M. van der Gevel and J. C. Kuenen, "Square-root X circuit based on a novel, back-gate-using multiplier." Electronics Letters, 30(3), pp. 183-184, February 1994.
30. M. H. Cohen and A. G. Andreou, "Analog CMOS integration and experimentation with an autoadaptive independent component analyzer." IEEE Transactions on Circuits and Systems: Part II: Analog and Digital Signal Processing, 42(2), pp. 65-77, February 1995.
31. T. S. Lande, J. A. Nesheim, and Y. Berg, "Auto correlation in micropower analog CMOS." Journal of Analog Integrated Circuits and Signal Processing, 7, pp. 61-68, January 1995.
32. E. A. Vittoz, "Analog VLSI implementation of neural networks." In Handbook of Neural Computation, Institute of Physics Publishing and Oxford University Press, USA.
33. B. L. Hart, "Translinear circuit principle: a reformulation." Electronics Letters, 15(24), pp. 801-803, Nov. 22, 1979.
34. Mead, C. A. and Mahowald, M. A., "A silicon model of early visual processing." Neural Networks, 1, pp. 91-97, 1988.
35. E. Vittoz and X. Arreguit, "Linear networks based on transistors." Electronics Letters, 29, pp. 297-299, February 4, 1993.
36. K. Bult and G. J. G. M. Geelen, "An inherently linear and compact MOST-only current division technique." IEEE J. Solid-State Circuit, SC-27(12), pp. 1730-1735, December 1992.
37. M. Tartagni and P. Perona, "Computing centroids in current-mode technique." Electronics Letters, 21, October 1993.
38. J. M. Buhmann, M. Lades, and R. Eeckman, "Illumination-invariant face recognition with a contrast sensitive silicon retina." In J. D. Cowan, G. Tesauro, and J. Alspector, eds., Advances in Neural Information Processing Systems 6. Morgan Kaufmann Publishers: San Mateo, CA, 1994.
39. J. E. Dowling, The Retina: An Approachable Part of the Brain. The Belknap Press of Harvard University: Cambridge, MA, 1987.
40. T. Poggio, V. Torre, and C. Koch, "Computational vision and regularization theory." Nature, 317, pp. 314-319, 1985.
41. C. A. Mead and T. Delbrück, "Scanners for visualizing activity in analog VLSI circuitry." Analog Integrated Circuits and Signal Processing, 1(2), Oct. 1991.
42. A. Pavasović, A. G. Andreou, and C. R. Westgate, "Characterization of subthreshold MOS mismatch in transistors for VLSI systems." Journal of Analog Integrated Circuits and Signal Processing, 6, pp. 75-84, June 1994.
43. B. Gilbert, "A monolithic 16-channel analog array normalizer." IEEE Journ. of Solid-State Circuits, SC-19(6), 1984.
44. B. Gilbert, "Nanopower nonlinear circuits based on the translinear principle." In Workshop on: Hardware implementation of neural nets and synapses, San Diego, CA, January 1988.
45. F. J. Pineda and A. G. Andreou, An Analog Neural Network Inspired by Fractal Block Coding, Advances in Neural Information Processing Systems, Vol. 7. Morgan Kaufmann Publishers: San Mateo, CA, 1995.
46. J. J. Ebers and J. L. Moll, "Large-signal behavior of junction transistors." Proceedings IRE, 42, pp. 1761-1772, December 1954.
47. R. S. Muller and T. I. Kamins, Device Electronics for Integrated Circuits. John Wiley and Sons: New York, 1977.
48. J. E. Meyer, "MOS models and circuit simulation." RCA Review, 32, pp. 42-63, March 1971.
49. Y. Tsividis, Operation and Modeling of the MOS Transistor. McGraw-Hill: New York, 1987.