A burst-mode word-serial address-event link - I: Transmitter design

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 51, Issue 7, 2004, Pages 1269-1280

  Boahen, Kwabena A ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTER PROGRAMMING; DATA COMMUNICATION SYSTEMS; DATA PROCESSING; ELECTRIC NETWORK SYNTHESIS; HIGH LEVEL LANGUAGES; INTEGRATED CIRCUIT LAYOUT; MULTIPLEXING; TELECOMMUNICATION LINKS; TRANSMITTERS;

ASYNCHRONOUS IMPLEMENTATION; ASYNCHRONOUS LOGIC CIRCUITS; COMMUNICATION CAPACITY; EVENT DRIVEN COMMUNICATION; FAIR ARBITER DESIGN; NEUROMORPHIC SYSTEMS; PARALLEL READOUT; PIXEL LEVEL QUANTIZATION; SCALABLE MULTIPLE ACCESS INTERCHIPLINK; TRANSMITTER DESIGN;

DIGITAL INTEGRATED CIRCUITS;

EID: 4043137376     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2004.830703     Document Type: Article

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