A learning-enabled neuron array IC based upon transistor channel models of biological phenomena

IEEE Transactions on Biomedical Circuits and Systems

Volumn 7, Issue 1, 2013, Pages 71-81

  Brink, Stephen ^a   Nease, Stephen ^a   Hasler, Paul ^a   Ramakrishnan, Shubha ^a   Wunderlich, Richard ^a   Basu, Arindam ^a   Degnan, Brian ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Electrical implementation of neurobiology; neuromorphic engineering

Indexed keywords

ADDRESS-EVENT REPRESENTATION; BIOLOGICAL COMPUTATIONS; BIOLOGICAL PHENOMENA; ELECTRICAL IMPLEMENTATION OF NEUROBIOLOGY; ELECTRONIC NEURONS; NEUROMORPHIC ENGINEERING; TESTING PLATFORMS; TRANSISTOR CHANNELS;

LEARNING ALGORITHMS; NEURAL NETWORKS;

NEURONS;

ARTICLE; ARTIFICIAL INTELLIGENCE; ARTIFICIAL NEURAL NETWORK; NERVE CELL; SEMICONDUCTOR; SYNAPSE;

ARTIFICIAL INTELLIGENCE; NEURAL NETWORKS (COMPUTER); NEURONS; SYNAPSES; TRANSISTORS, ELECTRONIC;

EID: 84875055083     PISSN: 19324545     EISSN: None     Source Type: Journal    
DOI: 10.1109/TBCAS.2012.2197858     Document Type: Article

References (32)

1. E. Farquhar, D. Abramson, and P. Hasler, "A reconfigurable bidirectional active 2 dimensional dendrite model," in Proc. Int. Symp. Circuits and Systems, May 2004, vol. 1, pp. 313-316
2. S. Nease, S. George, P. Hasler, S. Koziol, and S. Brink, "Modeling and implementation of voltage-mode CMOS dendrites on a reconfigurable analog platform," IEEE Trans. Biomed. Circuits Syst., vol. 6, no. 1, pp. 76-84, Feb. 2012
3. S. Saighi, Y. Bornat, J. Tomas, and S. Renaud, "A library of analog operators based on the Hodgkin-Huxley formalism for the design of tunable, real-time, silicon neurons," IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 1, pp. 3-19, Feb. 2011
4. J. Lin, P. Merolla, J. Arthur, and K. Boahen, "Programmable connections in neuromorphic grids," in Proc. IEEE Midwest Symp. Circuits and Symtems, 2006, pp. 80-84 (Pubitemid 47486800)
5. J. Schemmel, J. Fieres, and K. Meier, "Realizing biological spiking network models in a configurable wafer-scale hardware system," in Proc. IEEE Int. Joint Conf. Neural Networks, 2008, pp. 969-976
6. P. Hasler, C. Diorio, B.Minch, and C. Mead, "Single transistor learning synapse with long term storage," in Proc. IEEE Int. Symp. Circuits and Systems, May 1995, vol. 3, pp. 1660-1663
7. C. Gordon, E. Farquhar, and P. Hasler, "A family of floating-gate adapting synapses based upon transistor channel models," in Proc. Int. Symp Circuits and Systems, May 2004, vol. 1, pp. 317-320
8. S. Ramakrishnan, P. E. Hasler, and C. Gordon, "Floating gate synapses with spike time dependent plasticity," IEEE Trans. Biomed. Circuits Syst., vol. 5, no. 3, pp. 244-252, Jun. 2011
9. E. Farquhar and P. Hasler, "A bio-physically inspired silicon neuron," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 3, pp. 477-488, Mar. 2005 (Pubitemid 40466877)
10. A. Basu, S. Brink, C. Schlottmann, S. Ramakrishnan, C. Petre, S. Koziol, F. Baskaya, C. M. Twigg, and P. Hasler, "A floating-gate based field programmable analog array," IEEE J. Solid State Circuits, vol. 45, no. 9, pp. 1781-1794, Sep. 2010
11. A. Basu, S. Ramakrishnan, C. Petre, S. Koziol, S. Brink, and P. E. Hasler, "Neural dynamics in reconfigurable silicon," IEEE Trans. Biomed. Circuits Syst., vol. 4, no. 5, pp. 311-319, Oct. 2010
12. A. Basu and P. E. Hasler, "Nullcline based design of a silicon neuron," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 11, pp. 2938-2947, Nov. 2010
13. C. Twigg, J. Gray, and P. Hasler, "Programmable floating-gate FPAA switches are not dead weight," in Proc. Int. Symp. Circuits Syst., May 2007, pp. 169-72
14. D. Abramson, C. Schottmann, and P. Hasler, "Programmable and configurable MITE systems enabled through precise floating-gate programming," IEEE Trans. Circuits Syst. I, Reg. Papers, submitted for publication
15. A. Basu and P. E. Hasler, "A fully integrated architecture for fast and accurate programming of floating gates over six decades of current," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 6, pp. 953-962, 2011
16. S. Koziol, C. Schlottmann, A. Basu, S. Brink, C. Petre, S. Ramakrishnan, and P. Hasler, "Hardware and software infrastructure for a family of floating-gate FPAAs," in Proc. IEEE Int. Symp. Circuits and Systems , 2010
17. C. R. Schlottmann, C. Petre, and P. E. Hasler, "Simulink framework for design to and automated conversion on large-scale FPAA devices," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., submitted for publication
18. F. Baskaya, D. V. Anderson, P. Hasler, and S. K. Lim, "A generic reconfigurable array specification and programming environment (GRASPER)," in Proc. Eur. Conf. Circuit Theory and Design, Aug. 2009, pp. 619-622
19. C. Twigg and P. Hasler, "Incorporating large-scale FPAAs into analog design and test courses," IEEE Trans. Educ., vol. 51, no. 3, pp. 319-324, Aug. 2008
20. A. P. Davison, D. Brüderle, J. M. Eppler, J. Kremkow, E. Muller, D. A. Pecevski, L. Perrinet, and P. Yger, "PyNN: A common interface for neuronal network simulators," Front. Neuroinform, 2008
21. G. Indiveri, T. Horiuchi, E. Niebur, and R. Douglas, "A competitive network of spiking VLSI neurons," in Proc. World Congress Neuroinformatics, Vienna, Austria, Sep. 2001
22. C. Mead, Analog VLSI and Neural Systems. Reading, MA: Addison- Wesley, 1989
23. G.-Q. Bi and M. M. Poo, "Synaptic modifications in cultured hippocampal neurons: Dependence on spike timing, synaptic strength and post-synaptic cell type," J. Neurosci., vol. 18, pp. 10464-10472, 1998 (Pubitemid 29016566)
24. H. Markram, J. Lubke, M. Frotscher, and B. Sakmann, "Regulation of synaptic efficacy by coincidence of postsynaptic aps and epsps," Science, vol. 275, pp. 213-215, 1997 (Pubitemid 27034762)
25. L.Watts, D. Kerns, R. Lyon, and C. Mead, "Improved implementation of the silicon cochlea," IEEE J. Solid-State Circuits, vol. 27, no. 5, 1992
26. E. Neftci, E. Chicca, G. Indiveri, and R. Douglas, "A systematic method for configuring VLSI networks of spiking neurons," Neural Comput., vol. 23, no. 10, pp. 2457-2497, 2011
27. J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. A. Mead, "Winner-take-all networks of complexity," in Advances in Neural Information Processing Systems 1. San Mateo, CA: Morgan Kaufmann, 1989
28. H. B. Marr, B. Degnan, P. Hasler, and D. Anderson, "Minimization of energy per Op in an asynchronous pipeline above and below threshold," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., to be published
29. J. Schemmel, A. Grübl, K. Meier, and E. Muller, "Implementing synaptic plasticity in a VLSI spiking neural network model," in Proc. Int. Joint Conf. Neural Networks, Vancouver, BC, Canada, 2006, pp. 1-6 (Pubitemid 351369277)
30. J. Schemmel, J. Fieres, and K. Meier, "Wafer-scale integration of analog neural networks," in Proc. IEEE Int. Joint Conf. Neural Networks, Hong Kong, pp. 431-438
31. G. Indiveri, E. Chicca, and R. Douglas, "A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity," IEEE Trans. Neural Networks, vol. 17, no. 1, pp. 211-211, Jan. 2006
32. P. Camilleri, M. Giulioni, V. Dante, D. Badoni, G. Indiveri, B. Michaelis, J. Braun, and P. del Giudice, "A Neuromorphic aVLSI network chip with configurable plastic synapses," in Proc. 7th Int. Conf. Hybrid Intelligent Systems, 2007, pp. 296-301.