An event-based neural network architecture with an asynchronous programmable synaptic memory

IEEE Transactions on Biomedical Circuits and Systems

Volumn 8, Issue 1, 2014, Pages 98-107

  Moradi, Saber ^a   Indiveri, Giacomo ^a  

^a UNIVERSITY OF ZURICH   (Switzerland)

Author keywords

Address event representation (AER); analog digital; asynchronous; circuit; event based; learning; neural network; neuromorphic; programmable weights; real time; sensory motor; silicon neuron; silicon synapse; spike timing dependent plasticity (STDP); spiking; static random access memory (SRAM); synaptic dynamics; very large scale integration (VLSI)

Indexed keywords

DIGITAL CIRCUITS; NETWORK ARCHITECTURE; NETWORKS (CIRCUITS); NEURAL NETWORKS; NEURONS; SILICON; STATIC RANDOM ACCESS STORAGE; TIMING CIRCUITS; VLSI CIRCUITS;

ADDRESS-EVENT REPRESENTATION; ANALOG/DIGITAL; ASYNCHRONOUS; EVENT-BASED; LEARNING; NEUROMORPHIC; PROGRAMMABLE WEIGHTS; REAL-TIME; SENSORY-MOTOR; SILICON NEURON; SILICON SYNAPSE; SPIKE-TIMING-DEPENDENT PLASTICITY; SPIKING; STATIC RANDOM ACCESS MEMORY; SYNAPTIC DYNAMICS; VERY LARGE-SCALE INTEGRATION;

ASYNCHRONOUS SEQUENTIAL LOGIC;

ALGORITHM; ARTIFICIAL NEURAL NETWORK; BIOLOGICAL MODEL; ELECTRICAL EQUIPMENT; EQUIPMENT DESIGN; PHYSIOLOGY; SYNAPSE;

ALGORITHMS; ELECTRICAL EQUIPMENT AND SUPPLIES; EQUIPMENT DESIGN; MODELS, NEUROLOGICAL; NEURAL NETWORKS (COMPUTER); SYNAPSES;

EID: 84897963931     PISSN: 19324545     EISSN: None     Source Type: Journal    
DOI: 10.1109/TBCAS.2013.2255873     Document Type: Article

References (45)

1. W. Maass and E. Sontag, "Neural systems as nonlinear filters," Neural Comput., vol. 12, no. 8, pp. 1743-1772, 2000.
2. A. Belatreche, L. P. Maguire, and M. McGinnity, "Advances in design and application of spiking neural networks," Soft Comput., vol. 11, no. 3, pp. 239-248, Jan. 2006.
3. R. Brette, M. Rudolph, T. Carnevale, M. Hines, D. Beeman, J. Bower, M. Diesmann, A. Morrison, P. H. J. F. Goodman, M. Zirpe, T. Natschläger, D. Pecevski, B. Ermentrout, M. Djurfeldt, A. Lansner, O. Rochel, T. Vieville, E. Muller, A. Davison, S. El Boustani, and A. Destexhe, "Simulation of networks of spiking neurons: A review of tools and strategies," J. Comput. Neurosci., vol. 23, no. 3, pp. 349-398, Dec. 2007. (Pubitemid 47566522)
4. J. Brader, W. Senn, and S. Fusi, "Learning real world stimuli in a neural network with spike-driven synaptic dynamics," Neural Comput., vol. 19, pp. 2881-2912, 2007.
5. P. Rowcliffe and J. Feng, "Training spiking neuronal networks with applications in engineering tasks," IEEE Trans. Neural Netw., vol. 19, no. 9, pp. 1626-1640, Sep. 2008.
6. R. Serrano-Gotarredona, M. Oster, P. Lichtsteiner, A. Linares-Barranco, R. Paz-Vicente, F. Gómez-Rodriguez, L. Camunas-Mesa, R. Berner, M. Rivas-Perez, T. Delbruck, S.-C. Liu, R. Douglas, P. Häfliger, G. Jimenez-Moreno, A. Civit-Ballcels, T. Serrano-Gotarredona, A. Acosta-Jiménez, and B. Linares-Barranco, "CAVIAR: A 45 k neuron, 5 M synapse, 12 G connects/s are hardware sensory- processing-learning-actuating system for high-speed visual object recognition and tracking," IEEE Trans. Neural Netw., vol. 20, no. 9, pp. 1417-1438, Sep. 2009.
7. J. Wijekoon and P. Dudek, "Compact silicon neuron circuit with spiking and bursting behaviour," Neural Netw., vol. 21, no. 2-3, pp. 524-534, Mar.-Apr. 2008.
8. S. Millner, A. Grübl, K. Meier, J. Schemmel, and M.-O. Schwartz, "A VLSI implementation of the adaptive exponential integrate-and-fire neuron model," in Advances in Neural Information Processing Systems, J. Lafferty, C. K. I. Williams, J. Shawe-Taylor, R. Zemel, and A. Culotta, Eds. La Jolla, CA, USA: NIPS, 2010, vol. 23, pp. 1642-1650.
9. R. Silver, K. Boahen, S. Grillner, N. Kopell, and K. Olsen, "Neurotech for neuroscience: Unifying concepts, organizing principles, and emerging tools," J. Neurosci., vol. 27, no. 44, p. 11807, 2007.
10. X. Jin, M. Lujan, L. Plana, S. Davies, S. Temple, and S. Furber, "Modeling spiking neural networks on SpiNNaker," Comput. Sci. Eng., vol. 12, no. 5, pp. 91-97, Sep.-Oct. 2010.
11. J. V. Arthur, P. A. Merolla, F. Akopyan, R. Alvarez, A. Cassidy, A. Chandra, S. K. Esser, N. Imam, W. Risk, D. B. D. Rubin, R. Manohar, and D. S. Modha, "Building block of a programmable neuromorphic substrate: A digital neurosynaptic core," in Proc. IEEE Int. Joint Conf. Neural Networks, Jun. 2012, pp. 1946-1953.
12. N. Imam, F. Akopyan, J. Arthur, P. Merolla, R. Manohar, and D. Modha, "A digital neurosynaptic core using event-driven qdi circuits," in Proc. 18th IEEE Int. Symp. Asynchronous Circuits and Systems, May 2012, pp. 25-32.
13. Y.-X. Wang and S.-C. Liu, "Programmable synaptic weights for an aVLSI network of spiking neurons," in Proc. IEEE Int. Symp. Circuits and Systems, May 2006, pp. 4531-4534. (Pubitemid 47132563)
14. T. Pfeil, T. C. Potjans, S. Schrader, W. Potjans, J. Schemmel, M. Diesmann, and K. Meier, "Is a 4-bit synaptic weight resolution enough?-Constraints on enabling spike-timing dependent plasticity in neuromorphic hardware," Frontiers Neurosci. vol. 6, 2012.
15. J. Leñero-Bardallo, T. Serrano-Gotarredona, and B. Linares-Barranco, "A calibration technique for very low current and compact tunable neuromorphic cells. Application to 5-bit 20 nA DACs," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp. 522-526, Jun. 2008.
16. T. Yu and G. Cauwenberghs, "Analog VLSI biophysical neurons and synapses with programmable membrane channel kinetics," IEEE Trans. Biomed. Circuits Syst., vol. 4, no. 3, pp. 139-148, Jun. 2010.
17. T. Yu, J. Park, S. Joshi, C. Maier, and G. Cauwenberghs, "65 k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing," in Proc. IEEE Biomedical Circuits and Systems Conf., Nov. 2012, pp. 21-24.
18. S. Ramakrishnan, R. Wunderlich, and P. Hasler, "Neuron array with plastic synapses and programmable dendrites," in Proc. IEEE Biomedical Circuits and Systems Conf., Nov. 2012, pp. 400-403.
19. Y.Wang and S.-C. Liu, "Multilayer processing of spatiotemporal spike patterns in a neuron with active dendrites," Neural Comput., vol. 8, pp. 2086-2112, 2010.
20. A. Basu, S. Ramakrishnan, C. Petre, S. Koziol, S. Brink, and P. Hasler, "Neural dynamics in reconfigurable silicon," IEEE Trans. Biomed. Circuits Syst. vol. 4, no. 5, pp. 311-319, Oct. 2010.
21. P. Merolla, J. Arthur, B. Shi, and K. Boahen, "Expandable networks for neuromorphic chips," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 301-311, Feb. 2007. (Pubitemid 46444261)
22. E. Chicca, A. Whatley, P. Lichtsteiner, V. Dante, T. Delbruck, P. Del Giudice, R. Douglas, and G. Indiveri, "A multi-chip pulse-based neuromorphic infrastructure and its application to a model of orientation selectivity," IEEE Trans. Circuits Syst. I, Reg. Papers vol. 5, no. 54, pp. 981-993, 2007. (Pubitemid 46773770)
23. S. Scholze, S. Schiefer, J. Hartmann, C. Mayr, S. Höppner, H. Eisenreich, S. Henker, B. Vogginger, and R. Schüffny, "VLSI implementation of a 2.8 gevent/s packet based AER interface with routing and event sorting functionality," Frontiers Neurosci., vol. 5, no. 117, 2011.
24. S. Moradi and G. Indiveri, "A VLSI network of spiking neuronswith an asynchronous static random access memory," in Proc. IEEE Biomedical Circuits and Systems Conf., 2011, pp. 277-280.
25. S. Mitra, S. Fusi, and G. Indiveri, "Real-time classification of complex patterns using spike-based learning in neuromorphic VLSI," IEEE Trans. Biomed. Circuits Syst. vol. 3, no. 1, pp. 32-42, Feb. 2009.
26. M. Giulioni, M. Pannunzi, D. Badoni, V. Dante, and P. Del Giudice, "Classification of overlapping patterns with a configurable analog VLSI neural network of spiking neurons and self-regulating plastic synapses," Neural Comput., vol. 21, no. 11, pp. 3106-3129, 2009.
27. M. Valle, "Analog VLSI implementation of artificial neural networks with supervised on-chip learning," Anal. Integr. Circuits Signal Process., vol. 33, no. 3, pp. 263-287, 2002. (Pubitemid 35377398)
28. B.Wen and K. Boahen, "A silicon cochlea with active coupling," IEEE Trans. Biomed. Circuits Syst., vol. 3, no. 6, pp. 444-455, 2009.
29. S.-C. Liu and T. Delbruck, "Neuromorphic sensory systems," Current Opin. Neurobiol., vol. 20, no. 3, pp. 288-295, 2010.
30. K. Boahen, "Point-to-point connectivity between neuromorphic chips using address-events," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 5, pp. 416-34, 2000.
31. T.Delbruck and P. Lichtsteiner, "Fully programmable bias current generator with 24 bit resolution per bias," in Proc. IEEE Int. Symp. Circuits and Systems, 2006.
32. V. Ekanayake and R. Manohar, "Asynchronous DRAM design and synthesis," in Proc. 9th IEEE Int. Symp. Asynchronous Circuits and Systems, Vancouver, BC, Canada, May 2003, pp. 174-183.
33. G. Indiveri, B. Linares-Barranco, T. Hamilton, A. van Schaik, R. Etienne-Cummings, T. Delbruck, S.-C. Liu, P. Dudek, P. Häfliger, S. Renaud, J. Schemmel, G. Cauwenberghs, J. Arthur, K. Hynna, F. Folowosele, S. Saighi, T. Serrano-Gotarredona, J. Wijekoon, Y. Wang, and K. Boahen, "Neuromorphic silicon neuron circuits," Frontiers Neurosci. vol. 5, pp. 1-23, 2011.
34. M. Singh and S. Nowick, "High-throughput asynchronous pipelines for fine-grain dynamic datapaths," in Proc. IEEE 6th Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 2000, pp. 198-209.
35. A. Martin and M. Nystrom, "Asynchronous techniques for system-onchip design," Proc. IEEE, vol. 94, pp. 1089-1120, 2006.
36. P. Livi and G. Indiveri, "A current-mode conductance-based silicon neuron for address-event neuromorphic systems," in Proc. IEEE Int. Symp. Circuits and Systems, May 2009, pp. 2898-2901.
37. C. Bartolozzi and G. Indiveri, "Synaptic dynamics in analog VLSI," Neural Comput. vol. 19, no. 10, pp. 2581-2603, Oct. 2007.
38. C. Bartolozzi, S. Mitra, and G. Indiveri, "An ultra low power current- mode filter for neuromorphic systems and biomedical signal processing," in Proc. IEEE Biomedical Circuits and Systems Conf., 2006, pp. 130-133.
39. S.-C. Liu, J. Kramer, G. Indiveri, T. Delbruck, and R. Douglas, Analog VLSI: Circuits and Principles. Cambridge, MA, USA: MIT Press, 2002.
40. A. Rauch, G. L. Camera, H.-R. Luescher, W. Senn, and S. Fusi, "Neocortical pyramidal cells respond as integrate-and-fire neurons to in vivo-like input currents," J. Neurophysiol., vol. 79, 2003.
41. D. Madison and R. Nicoll, "Control of the repetitive discharge of rat CA 1 pyramidal neurones in vitro," J. Physiol., vol. 354, no. 1, pp. 319-331, 1984. (Pubitemid 14066369)
42. E. Izhikevich, "Simple model of spiking neurons," IEEE Trans. Neural Netw., vol. 14, no. 6, pp. 1569-1572, 2003.
43. R. Brette and W. Gerstner, "Adaptive exponential integrate-and-fire model as an effective description of neuronal activity," J. Neurophysiol., vol. 94, pp. 3637-3642, 2005. (Pubitemid 41504797)
44. R. Naud, N. Marcille, C. Clopath, and W. Gerstner, "Firing patterns in the adaptive exponential integrate-and-fire model," Biolog. Cybern., vol. 99, no. 4-5, pp. 335-347, Nov. 2008.
45. L. Badel, S. Lefort, R. Brette, C. Petersen, W. Gerstner, and M. Richardson, "Dynamic i-v curves are reliable predictors of naturalistic pyramidal-neuron voltage traces," J. Neurophysiol., vol. 99, pp. 656-666, 2008. (Pubitemid 351253226)