Scalable network-on-chip architecture for configurable neural networks

Microprocessors and Microsystems

Volumn 35, Issue 2, 2011, Pages 152-166

  Vainbrand, Dmitri ^a   Ginosar, Ran ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Hardware implementation; Interconnect architecture; Networks on Chip; Reconfigurable neural networks

Indexed keywords

ANALYTICAL EVALUATION; ANALYTICAL EXPRESSIONS; ANALYTICAL MODEL; ASYMPTOTIC BEHAVIORS; ASYMPTOTIC LIMITS; COMMUNICATION METHOD; CONFIGURABLE; HARDWARE IMPLEMENTATIONS; HIERARCHICAL ARCHITECTURES; INTERCONNECT ARCHITECTURES; MULTICAST MESH; MULTICASTS; NETWORKS ON CHIP; NEURAL NETWORK TOPOLOGY; PERFORMANCE/COST RATIO; RE-CONFIGURABLE; ROUTING TABLE; SCALABLE NETWORKS; SHARED BUS; SIMULATION RESULT; UNICAST;

ASYMPTOTIC ANALYSIS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC NETWORK TOPOLOGY; HARDWARE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; MESH NETWORKING; MULTICASTING; NEURAL NETWORKS; RECONFIGURABLE HARDWARE; TELECOMMUNICATION SYSTEMS; VLSI CIRCUITS; WIRELESS SENSOR NETWORKS;

NETWORK ARCHITECTURE;

EID: 79951906654     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2010.08.005     Document Type: Article

References (39)

1. R. Legenstein, and W. Maass Edge of chaos and prediction of computational performance for neural microcircuit models Neural Networks 20 3 2007 323 334 (Pubitemid 46856111)
2. C. Leiserson Fat-Trees: universal networks for hardware-efficient supercomputing IEEE Transactions on Computers C-34 10 1985 892 901 (Pubitemid 16574278)
3. S.R. Ohring, M. Ibel, S.K. Das, M.J. Kumar, On generalized fat-tree, in: Proceedings of the International Conference on Supercomputing, 1995, pp. 276-285.
4. R. Rojas Neural Networks: A Systematic Introduction 1996 Springer-Verlag Berlin pp. 338-371 (Chapter 13)
5. W. Maass Networks of spiking neurons: the third generation of neural network models Neural Networks 10 9 1997
6. T. Morie, M. Nagata, A. Iwata, Design of a pixel-parallel feature extraction VLSI system for biologically-inspired object recognition method, in: Proceedings of the International Symposium on Nonlinear Theory and its Application, 2001, pp. 371-374.
7. J. Schreiter et al., Cellular pulse coupled neural network with adaptive weights for image segmentation and its VLSI implementation, in: Proceedings of the International Symposium on Electronic Imaging: Science and Technology, vol. 5298, 2004, pp. 290-296.
8. G. Indiveri, E. Chicca, R. Douglas, A VLSI reconfigurable network of integrate-and-fire neurons with spike-based learning synapses, in: Proceedings of the European Symposium on Artificial Neural Networks, 2004, pp. 405-410.
9. C. Mayr large-scale spiking neural networks on VLSI International Journal of Applied Science Engineering and Technology 4 1 2007
10. A. Mortara, E. Vittoz, and P. Vanier A communication scheme for analog VLSI perceptive systems IEEE JSSC 30 6 1995 660 669
11. K.A. Boahen Point-to-point connectivity between neuromorphic chips using address events IEEE Transactions Circuits and Systems 47 5 2000
12. S.C. Liu Orientation-selective VLSI spiking neurons Neural Networks 14 2001 629 643
13. J. Lazzaro, J. Wawrzynek, A multi-sender asynchronous extension to the AER protocol, in: Proceedings of the Conference on Advanced Research in VLSI, 1995, pp. 158-169.
14. W.J. Dally, B. Towles, Route packets not wires: on-chip interconnection networks, in: Proceedings of the 38th Design Automation Conference, 2001, pp. 684- 689. (Pubitemid 32841038)
15. A. Jantsch, Networks on Chip, Workshop at the European Solid State Circuits Conference, 2001.
16. L. Benini, and G. De Micheli Networks on chips: a new SoC paradigm IEEE Computer 35 2002 70 78 (Pubitemid 34069383)
17. T. Theocharides, G. Link, N. Vijaykrishnan, M.J. Irwin, A generic reconfigurable neural network architecture as a network on chip, in: Proceedings of the International SOC Conference, 2004, p. 191.
18. L.A. Plana, and S.B. Furber A GALS infrastructure for a massively parallel multiprocessor IEEE Design & Test of Computers 24 5 2007 454 463 (Pubitemid 47577894)
19. R. Emery, A. Yakovlev, G. Chester, Connection-centric network for spiking neural networks, in: Proceedings of the NOCS, 2009, pp. 144-152.
20. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny Cost considerations in Network on Chip Integration 38 1 2004 19 42
21. S. McCanne, S. Floyd, ns Network Simulator. < http://www.isi.edu/ nsnam/ns/ >.
22. N. Eisley, L.S. Peh, High-level power analysis for on-chip networks, in: Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, 2004, pp. 104-115. (Pubitemid 41802772)
23. U.Y. Ogras, R. Marculescu, Analytical router modeling for Networks-on-Chip performance analysis, in: Proceedings of the DATE, 2007, pp. 1096-1101. (Pubitemid 47334106)
24. F. Gilabert, S. Medardoni, D. Bertozzi, L. Benini, et al., Exploring high-dimensional topologies for NoC design through an integrated analysis and synthesis framework, in: Proceedings of the NOCS, 2008, pp. 107-116. (Pubitemid 351715035)
25. A. Banerjee, R. Mullins, S. Moore, A power and energy exploration of Network-on-Chip architectures, in: Proceedings of the NOCS, 2007, pp. 163-172. (Pubitemid 350153589)
26. D. Peleg, and E. Upfal A trade-off between space and efficiency for routing tables Journal of the Association for Computing Machinery 36 1989 510 530
27. J. Van Leeuwen, and R.B. Tan Interval routing The Computer Journal 30 1987 298 307
28. M.E. Gómez et al., A memory-effective routing strategy for regular interconnection networks, IPDPS, 2005.
29. E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, Routing table minimization for irregular mesh NoCs, in: Proceedings of the Design, Automation and Test in Europe Conference, April 2007, pp. 942-947. (Pubitemid 47334080)
30. W.S. McCulloch, and W. Pitts A logical calculus of the ideas immanent in nervous activity Bulletin of Mathematical Biophysics 5 1943
31. W. Maass, and C.M. Bishop Pulsed Neural Networks 1999 MIT Press Cambridge, MA (Chapters 1, 2, and 4)
32. E.M. Izhikevich Which model to use for cortical spiking neurons? IEEE Transactions on Neural Networks 15 5 2004
33. J.G. Milton, Dynamics of small neural populations, American Mathematical Society, Providence, RI, 1996 (Chapter 8).
34. D. Goldberg, G. Cauwenberghs, A. Andreou, Analog VLSI spiking neural network with address domain probabilistic synapses, in: Proceedings of the IEEE International Symposium Circuits and Systems (ISCAS2001), IEEE Press, 2001, pp. 241-244. (Pubitemid 32469837)
35. Ulrich Ramacher SYNAPSE: a neurocomputer that synthesizes neural algorithms on a parallel systolic engine Journal of Parallel and Distributed Computing 14 3 1992 306 318
36. C. Johansson, and A. Lansner Towards cortex sized artificial neural systems Neural Networks 20 2007 48 61 (Pubitemid 44960619)
37. M.J. Pertel, Mesh Distance Formulae, Technical Report, California Institute of Technology (CaltechCSTR:1992.cs-tr-92-05).
38. A. Jantsch, and H. Tenhunen Networks on Chip 2003 Kluwer Academic Publishers Hingham, MA
39. K. Goossens Guaranteeing the quality of services in networks on chip Networks on Chip 2003 Kluwer Academic Publishers Hingham, MA