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Volumn , Issue OCT, 2011, Pages

VLSI implementation of a 2.8 Gevent/s packet-based AER interface with routing and event sorting functionality

Author keywords

Configurable pulse delays; Configuration over AER; Packet based AER; Serial AER inVLSI

Indexed keywords

ARTICLE; BRAIN CORTEX; INTERPERSONAL COMMUNICATION; NERVE CELL NETWORK; NEUROANATOMY; NEUROTRANSMISSION;

EID: 84862237704     PISSN: 16624548     EISSN: 1662453X     Source Type: Journal    
DOI: 10.3389/fnins.2011.00117     Document Type: Article
Times cited : (43)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.