Asynchronous techniques for system-on-chip design

Proceedings of the IEEE

Volumn 94, Issue 6, 2006, Pages 1089-1120

  Martin, Alain J ^a,b   Nyström, Mika ^a,b  

^a IEEE   (United States)

^b CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Arbiter; Asynchronous; Asynchronous bus; Asynchronous synchronous interface; C element; Completion tree; Dual rail; Globally asynchronous and locally synchronous (GALS); Half buffer; Handshake protocol; Isochronic fork; Metastability; Passive active buffer

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTATIONAL COMPLEXITY; DECISION TREES; FUNCTION EVALUATION; SIGNAL PROCESSING; TELECOMMUNICATION NETWORKS;

ARBITER; ASYNCHRONOUS BUS; ASYNCHRONOUS/SYNCHRONOUS INTERFACE; C-ELEMENT; COMPLETION TREE; GLOBALLY ASYNCHRONOUS AND LOCALLY SYNCHRONOUS (GALS); HANDSHAKE PROTOCOL; ISOCHRONIC FORK; METASTABILITY; PASSIVE-ACTIVE BUFFER;

SYSTEMS ANALYSIS;

EID: 33947432403     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2006.875789     Document Type: Article

References (58)

1. The "asynchronous" bibliography. (2004). [Online]. Available: http://www.win.tue.nl/async-bib/
2. H. C. Brearley, "ILLIAC II: A short description and annotated bibliography," IEEE Trans. Comput., vol. C-14, no. 6, pp. 399-403, Jun. 1965.
3. C. H. K. v. Berkel and R. Saejis, "Compilation of communicating processes into delay-insensitive circuits," Proc. Int. Conf. Computer Design (ICCD), 1988, pp. 157-162.
4. E. Brunvand and R. F. Sproull, "Translating concurrent programs into delay-insensitive circuits," Dig. Tech. Papers 1989 IEEE Int. Conf. Computer-Aided Design, pp. 262-265.
5. S. M. Bums and A. J. Martin, "Syntax-directed translation of concurrent programs into self-timed circuits," in Advanced Research in VLSI, J. Allen and F. Leighton, Eds. Cambridge, MA: MIT Press, 1988.
6. T. J. Chaney and C. E. Molnar, "Anomalous behavior of synchronizer and arbiter circuits," IEEE Trans. Comput., vol. C-22, no. 4, pp. 421-422, Apr. 1973.
7. D. M. Chapiro, Globally-Asynchronous, Locally-Synchronous Systems, Ph.D. dissertation, Stanford Univ., Stanford, CA, 1984, Stanford CS Tech. Rep. STAN-CS-84-1026.
8. T.-A. Chu, "Synthesis of self-timed VLSI circuits from graph-theoretic specifications," in Proc. Int. Conf. Computer Design (ICCD), 1987, pp. 220-223.
9. F.-C. Cheng, "Practical design and performance evaluation of completion detection circuits," in IEEE Int. Conf. Computer Design (ICCD), 1998, pp. 354-359.
10. W. A. Clark, "Macromodular computer systems," in AFIPS Conf. Proc. 1967 Spring Joint Computer Conf., 1967, pp. 335-336.
11. J. Cortadella et al. Logic Synthesis of Asynchronous Controllers and Interfaces. New York: Springer-Verlag, 2002.
12. _, "Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers," IEICE Trans. Inf. Syst., vol. E80-D, pp. 315-325, 1997.
13. W. J. Dally and J. W. Poulton, Digital Systems Engineering. Cambridge, U.K.: Cambridge Univ. Press, 1998.
14. S. B. Furber et al., "A micropipelined ARM," in Proc. VII Banff Workshop: Asynchronous Harolu-are Design, 1993.
15. _, "AMULET2e: An asynchronous embedded controller," in Proc. Async '97, 1997, pp. 290-299.
16. J. D. Garside, "Processors," in Principles of Asynchronous Circuit Design: A Systems Perspective, J. Sparse and S. Furber, Eds. Boston, MA: Kluwer, 2001, ch. 15.
17. H. v. Gageldonk et al., "An asynchronous low-power 80c51 microcntroller," Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 1999, pp. 96-107.
18. M. R. Greenstreet, "Real-time merging," in Proc. Fifth Int. Symp. Advanced Research in Asynchronous Circuits and Systems: ASYNC99, Barcelona, Spain, 19-21 April 1999, Los Alamitos, CA: IEEE CS Press, 1999.
19. C. A. R. Hoare, "Communicating sequential processes," Commun. ACM, vol. 21, pp. 666-677, 1978.
20. D. A. Huffman, "The synthesis of sequential switching circuits," in Sequential Machines: Selected Papers, E. F. Moore, Ed. Reading, MA: Addison-Wesey, 1964.
21. C. Kelly, IV, V. Ekanyake, and R. Manohar, "SNAP: A sensor network asynchronous processor," Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 2003, pp. 24-35.
22. A. M. Lines, "Pipelined asynchronous circuits," M.S. thesis, California Inst. Technol., Pasadena, 1997.
23. R. Manohar and A. J. Martin, "Quasi-delay-insensitive circuits are turing-complete," Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, Fukushima, Japan, 1996.
24. A. J. Martin, "The design of a self-timed circuit for distributed mutual exclusion," Proc. 1985 Chapel Hill Conf. VLSI, H. Fuchs, Ed., pp. 245-260.
25. _, "Programming in VLSI: From communicating processes to self-timed VLSI circuits," in Concurrent Programming (1987 UT Year of Programming Institute on Concurrent Programming), C. A. R. Hoare, Ed. Reading, MA.: Addison-Wesley, 1989.
26. _, "The limitations to delay-insensitivity in asynchronous circuits," Proc. 6th MIT Conf. Advanced Research in VLSI, W. J. Dally, Ed., 1990, pp. 263-278.
27. A. J. Martin et al., "The design of an asynchronous microprocessor," Proc. Decennial Caltech Conf. Advanced Research in VLSI, C. L. Seitz, Ed., 1991, pp. 351-373.
28. _, "The Design of an Asynchronous MIPS R3000 Processor," in Proc. 17th Conf. Advanced Research in VLSI, Los Alamitos, CA: IEEE CS Press, 1997.
29. A. J. Martin, "Synthesis method for self-timed VLSI circuits," in Proc. 1987 IEEE Int. Conf. Computer Design (ICCD 87), pp. 224-229.
30. A. J. Martin, M. Nyström, and C. G. Wong, "Three generations of asynchronous microprocessors," IEEE Des. Test Comput. (Special Issue on Clockless VLSI Design), vol. 20, no. 6, pp. 9-17, Nov./Dec. 2003.
31. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980.
32. R. E. Miller, Switching Theory. New York: Wiley, 1965, vol. 2, ch. 10.
33. D. E. Muller and W. S. Bartky, "A theory of asynchronous circuits," Proc. Int. Symp. Theory of Switching, 1959, pp. 204-243.
34. C. J. Myers, Asynchronous Circuit Design. New York: Wiley, 2001.
35. J. Muttersbach, T. Villiger, and W. Fichner, "Practical design of globally-asynchronous locally-synchronous systems," Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 2000, pp. 52-59.
36. T. Nanya et al., "TITAC: Design of a quasi-delay-insensitive microprocessor," IEEE Des. Test Comput., vol. 11, no. 2, pp. 50-63, Summer, 1994, IEEE.
37. _, "TITAC-2: A 32-bit scalable-delay-insensitive microprocessor," in Proc. HOT Chips IX, 1997, pp. 19-32.
38. S. M. Nowick, M. B. Josephs, and C. H. van Berkel, "Special issue: Asynchronous circuits and systems," Proc. IEEE, vol. 87, no. 2, pp. 217-396, 1999.
39. M. Nyström and A. J. Martin, "Crossing the synchronous- asynchronous divide," presented at the Workshop Complexity Effective Design, Anchorage, AK, 2002.
40. _, Asynchronous Pulse Logic. Boston, MA: Kliwer, 2001.
41. P. Prakash and A. J. Martin, "Slack matching quasi-delay-insensitive circuits," in Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 2006, pp. 195-204.
42. M. Renaudin, P. Vivet, and F. Robin, "ASPRO-216: A standard-cell QDI 16-bit RISC asynchronous microprocessor," Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 1998, pp. 22-31.
43. F. U. Rosenberger, C. E. Molnar, T. J. Chaney, and T.-P. Fang, "Q-modules: internally clocked delay-insensitive modules," IEEE Trans. Comput., vol. 37, no. 9, pp. 1005-1018, Sep. 1988.
44. S. Rotem et al., "RAPPID: An asynchronous instruction length decoder," Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 1999, pp. 60-70.
45. C. L. Seitz, "System timing," in Introduction to VLSI Systems. Reading, MA: Addison-Wesley, 1980, ch. 7.
46. J. Sparso and S. Furber, Eds., Principles of Asynchronous Circuit Design: A Systems Perspective. Boston, MA: Kluwer, 2001.
47. M. J. Stucki and J. J. Cox, "Synchronization strategies," in Proc. 1st Caltech Conf. Very Large Scale Integration, C. L. Seitz, Ed., 1979, pp. 375-393.
48. I. E. Sutherland and S. Fairbanks, "GasP: A minimal FIFO control," in Proc. 10th Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 2004, pp. 46-53.
49. T. E. Williams and M. A. Horovritz, "A zero-overhead self-timed 160 ns 54 b CMOS divider," IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1651-1661, Nov. 1991.
50. PDP-11 Peripherals and Interfacing Handbook, Digital Equipment Corp., Maynard, MA, 1971, DEC part no. 112-01071-1854 D-09-25.
51. PDP-11 Bus Handbook, Digital Equipment Corp., Maynard, MA, 1979, DEC part no. EB-17525-20/79 070-14-55.
52. Arithmetic Processor 166 Instruction Manual, Digital Equipment Corp., Maynard, MA, 1960.
53. S. H. Unger, Asynchronous Sequential Switching Circuits. New York: Wiley, 1969.
54. Small computer system interface - 2, Tech. Comm. T10, Amer. Nat. Stand. Inst., Draft report X3T9.2/86-109, 1989.
55. C. G. Wong and A. J. Martin, "High-level synthesis of asynchronous systems by data-driven decomposition," in Proc. ACM/IEEE Design Automation Conf., 2003, pp. 508-513.
56. L. A. Glasser and D. W. Dobberpuhl, The Design and Analysis of VLSI Circuits. Reading, MA: Addison-Wesley, 1985.
57. T. Chelcea and S. M. Nowick, "Robust interfaces for mixed-timing systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 8, pp. 857-873, Aug. 2004.
58. F. K. G̈rkaynak et al., "GALS at ETH Zurich: Success or failure?" in Proc. Int. Symp. Advanced Research in Asynchronous Circuits and Systems, 2006, pp. 150-159.