Noise-immune embedded NAND-ROM using a dynamic split source-line scheme for VDDmin and speed improvements

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 10, 2010, Pages 2142-2155

  Chang, Meng Fan ^a   Yang, Shu Meng ^a   Liang, Chih Wei ^a   Chiang, Chih Chyuang ^a   Chiu, Pi Feng ^a   Lin, Ku Feng ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Crosstalk; low voltage; NAND ROM; ROM

Indexed keywords

AREA PENALTY; BITLINES; CELL ARRAY; GATE-LEAKAGE CURRENT; HIGH-RELIABILITY; LOGIC PROCESS; LOW SUPPLY VOLTAGES; LOW VOLTAGES; NAND-ROM; NON-VOLATILE; ON CHIPS; READ ACCESS TIME; READ NOISE; SENSING MARGIN; SPEED IMPROVEMENT; SUPPLY VOLTAGES;

CROSSTALK; LEAKAGE CURRENTS;

ROM;

EID: 77957581386     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2060279     Document Type: Conference Paper

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