An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 3, 2001, Pages 510-515

  Noda, K ^a   Takeda, K ^a   Matsui, K ^a   Ito, S ^a   Masuoka, S ^a   Kawamoto, H ^a   Ikezawa, N ^a   Aimoto, Y ^a   Nakamura, N ^a   Iwasaki, T ^a   Toyoshima, H ^a   Horiuchi, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; MACROS; MOSFET DEVICES;

ULTRAHIGH DENSITY HIGH SPEED LOADLESS FOUR TRANSISTORS;

STATIC RANDOM ACCESS STORAGE;

EID: 0035273853     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.910490     Document Type: Article

References (8)

1. 2 loadless CMOS four-transistor SRAM cell in a 0.18-μm logic technology
2. 2 embedded SRAM cell with Co-salicide direct-strap technology for 0.18-μm high-performance CMOS logic
3. A 400-MHz 16-Mb loadless CMOS four-transistor SRAM macro
4. A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro
5. Integration of trench DRAM into a high-performance 0.18-μm logic technology with copper BEOL
6. 2 stacked capacitor cell
7. 2 stacked DRAM technology integrated with high-performance 0.2-μm CMOS logic and six-level metallization