A 1.6 GB/s DDR2 128 Mb chain FeRAM with scalable octal bitline and sensing schemes

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 1, 2010, Pages 142-152

  Shiga, Hidehiro ^a   Takashima, Daisaburo ^a   Shiratake, Shin Ichiro ^a   Hoya, Katsuhiko ^a   Miyakawa, Tadashi ^a   Ogiwara, Ryu ^a   Fukuda, Ryo ^a   Takizawa, Ryosuke ^a   Hatsuda, Kosuke ^a   Matsuoka, Fumiyoshi ^a   Nagadomi, Yasushi ^a   Hashimoto, Daisuke ^a   Nishimura, Hisaaki ^a   Hioka, Takeshi ^a   Doumae, Sumiko ^a   Shimizu, Shoichi ^b   Kawano, Mitsumo ^b   Taguchi, Toyoki ^b   Watanabe, Yohji ^a   Fujii, Shuso ^a   Ozaki, Tohru ^a   Kanaya, Hiroyuki ^a   Kumura, Yoshinori ^a   Shimojo, Yoshiro ^a   Yamada, Yuki ^a   Minami, Yoshihiro ^a   Shuto, Susumu ^a   Yamakawa, Koji ^a   Yamazaki, Soichi ^a   Kunishima, Iwao ^a   Hamamoto, Takeshi ^a   Nitayama, Akihiro ^a   Furuyama, Tohru ^a   more..

^a TOSHIBA CORPORATION   (Japan)

^b AC Technologies Corporation   (Japan)

Author keywords

FeRAM; Ferroelectric memory; Nonvolatile memory; RAM; Random access memory

Indexed keywords

AREA PENALTY; BIT-LINE ANDS; BIT-LINE ARCHITECTURE; BITLINE CAPACITANCE; CELL SIGNALS; CELL SIZE; CONVENTIONAL LASERS; CURRENT DRIVERS; EVENT DRIVEN; FERROELECTRIC MEMORY; MEMORY CELL; METAL CMOS PROCESS; NON-VOLATILE MEMORIES; PARASITIC CAPACITANCE; POWER LINES; RANDOM ACCESS MEMORIES; SENSING SCHEMES;

CAPACITANCE; ELECTRIC POTENTIAL; FERROELECTRIC DEVICES; FERROELECTRICITY; VOLTAGE REGULATORS;

RANDOM ACCESS STORAGE;

EID: 73249152995     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2034414     Document Type: Conference Paper

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