0.9-ns-access, 700-MHz SRAM macro using a configurable organization technique with an automatic timing adjuster

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1998, Pages 182-183

  Ando, Kazumasa ^a   Higeta, Keiichi ^a   Fujimura, Yasuhiro ^a   Mori, Kazutaka ^a   Nakayama, Michiaki ^a   Nambu, Hiroaki ^a   Miyamoto, Kazuhisa ^a   Yamaguchi, Kunihiko ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; TIMING CIRCUITS;

BACK BIAS CONTROL CIRCUITS; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0031637809     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)