A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 11, 1998, Pages 1650-1657

  Nambu, Hiroaki ^a,d,e   Kanetani, Kazuo ^a,e   Yamasaki, Kaname ^a,e,f   Higeta, Keiichi ^a   Usami, Masami ^a   Fujimura, Yasuhiro ^a   Ando, Kazumasa ^a   Kusunoki, Takeshi ^a   Yamaguchi, Kunihiko ^a   Homma, Noriyuki ^b,c  

^a HITACHI LTD   (Japan)

^b HOSEI UNIVERSITY   (Japan)

^c IEEE

^d YOKOHAMA NATIONAL UNIVERSITY   (Japan)

^e Inst Electronics Info Commun E   (Japan)

^f TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Activation pulse generator; Cache memory; Clock access time; Cycle time; Decoder; Duplicate memory cell; Memory cell; Power dissipation; Reset circuit; Sense amplifier; Source coupled logic; SRAM; Timing margin.

Indexed keywords

BUFFER STORAGE; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; DECODING; LOGIC CIRCUITS; PULSE GENERATORS;

CLOCK-ACCESS TIME; DECODER CIRCUITS; RESET CIRCUITS; SOURCE-COUPLED LOGIC (SCL); STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0032205465     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.726553     Document Type: Article

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