A 0.9-V 1T1C SBT-based embedded nonvolatile FeRAM with a reference voltage scheme and multilayer shielded bit-line structure

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 1, 2005, Pages 286-292

  Yamaoka, Kunisato ^a   Iwanari, Shunichi ^a   Murakuki, Yasuo ^a   Hirano, Hiroshige ^a   Sakagami, Masahiko ^a   Nakakuma, Tetsuji ^a   Miki, Takashi ^a   Gohou, Yasushi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

Ferroelectric; Imprint; Memory; Nonvolatile; One transistor one capacitor (1T1C); Reference voltage

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITANCE; CAPACITORS; ELECTRIC POTENTIAL; FERROELECTRIC DEVICES; LSI CIRCUITS; MULTILAYERS; PRODUCT DESIGN; SCANNING ELECTRON MICROSCOPY; TRANSISTORS;

IMPRINT; NONVOLATILE MEMORY; ONE-TRANSISTOR ONE-CAPACITOR (1T1C) SBT; REFERENCE VOLTAGE;

RANDOM ACCESS STORAGE;

EID: 11944273158     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.837967     Document Type: Conference Paper

References (5)

1. Y. Chung et al., "A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme," in Symp. VLSI Circuits Dig. Tech. Papers, 1999, pp. 97-98.
2. J. Yamada et al., "A self-reference read scheme for a 1T/1C FeRAM," in Symp. VLSI Circuits Dig. Tech. Papers, 1998, pp. 238-241.
3. H. Hirano et al., "2 V/100 ns 1T/1C nonvolatile ferroelectric memory architecture with bitline-driven read scheme & nonrelaxation reference cell," in Symp. VLSI Circuits Dig. Tech. Papers, 1996, pp. 48-49.
4. T. Sumi et al., "A 0.9 V embedded ferroelectric memory for microcontrollers," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1995, pp. 70-71.
5. T. S. Moise et al., "Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process," in IEDM Tech. Dig., 2002, pp. 535-538.