A study of self-aligned nitride erasable OTP cell by 45-nm CMOS fully compatible process

IEEE Transactions on Electron Devices

Volumn 56, Issue 6, 2009, Pages 1228-1234

  Huang, Chia En ^a   Chen, Ying Je ^b   Lai, Han Chao ^a   King, Ya Chin ^a   Lin, Chrong Jung ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b EMEMORY TECHNOLOGY INC   (Taiwan)

Author keywords

Logic compatible; Nonvolatile memory (NVM); P channel; Self aligned nitride (SAN)

Indexed keywords

CELL SIZE; CMOS TECHNOLOGY; DATA RETENTION; FULLY COMPATIBLE; GATE LENGTH; INJECTION PROGRAMMING; LOGIC COMPATIBLE; LOGIC NVM; NON-VOLATILE MEMORIES; NONVOLATILE MEMORY (NVM); ONE-TIME PROGRAMMING; OPERATIONAL CONDITIONS; P-CHANNEL; PROGRAM EFFICIENCY; SELF-ALIGNED NITRIDE; SELF-ALIGNED NITRIDE (SAN); STORAGE NODES; STORED CHARGE;

CMOS INTEGRATED CIRCUITS; NITRIDES; NONVOLATILE STORAGE;

CELLS;

EID: 67349137724     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2018169     Document Type: Article

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