A 34 MB/s MLC write throughput 16 Gb NAND with all bit line architecture on 56 nm technology

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 186-194

  Cernea, Raul Adrian ^a   Pham, Long ^a   Moogat, Farookh ^a   Chan, Siu ^a   Le, Binh ^a   Li, Yan ^a   Tsao, Shouchang ^a   Tseng, Tai Yuan ^a   Nguyen, Khanh ^a   Li, Jason ^a   Hu, Jayson ^a   Yuh, Jong Hak ^a   Hsu, Cynthia ^a   Zhang, Fanglin ^a   Kamei, Teruhiko ^a   Nasu, Hiroaki ^a   Kliza, Phil ^a   Htoo, Khin ^a   Lutze, Jeffrey ^a   Dong, Yingda ^a   Higashitani, Masaaki ^a   Yang, Junnhui ^a   Lin, Hung Szu ^a   Sakhamuri, Vamshi ^a   Li, Alan ^a   Pan, Feng ^a   Yadala, Sridhar ^a   Taigor, Subodh ^a   Pradhan, Kishan ^a   Lan, James ^a   Chan, James ^a   Abe, Takumi ^b   Fukuda, Yasuyuki ^b   Mukai, Hideo ^b   Kawakami, Koichi ^b   Liang, Connie ^a   Ip, Tommy ^a   Chang, Shu Fen ^a   Lakshmipathi, Jaggi ^a   Huynh, Sharon ^a   Pantelakis, Dimitris ^a   Mofidi, Mehrdad ^a   Quader, Khandker ^a   more..

^a SanDisk Corporation   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

4 state; 56 nm; All bitline (ABL); Architecture; Current sensing; Flash memory; MLC chip; NAND; Performance; Throughput

Indexed keywords

ARCHITECTURE; NETWORKS (CIRCUITS); THROUGHPUT; TROPOSPHERE;

4-STATE; 56 NM; ALL BITLINE (ABL); CURRENT SENSING; MLC CHIP; NAND; PERFORMANCE;

FLASH MEMORY;

EID: 58149267843     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007152     Document Type: Conference Paper

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