A commercial field-programmable dense eFUSE array memory with 99.999% sense yield for 45nm SOI CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 406-407

  Uhlmann, Greg ^a   Aipperspach, Tony ^a   Kirihata, Toshiaki ^a   Kothandaraman, Chandrasekharan ^a   Li, Yan Zun ^a   Paone, Chris ^a   Reed, Brian ^a   Robson, Norman ^a   Safran, John ^a   Schmitt, David ^a   Iyer, Subramanian ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

FIELD PROGRAMMABLES; ONE-TIME PROGRAMMABLES; READ OPERATION; SOI CMOS; TEST CHIPS; VLSI DESIGN;

CMOS INTEGRATED CIRCUITS;

EID: 49549084181     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523229     Document Type: Conference Paper

References (5)

1. R. Rizzolo, T. Foote, J. Crafts et al., "IBM System z9 eFUSE Applications and Methodology," IBM J. Res. Dev., vol. 51, no. 1/2, pp. 65-75, Jan./Mar. 2007.
2. J. Barth, D. Anand, J. Dreibelbis et al., "A 500MHz Multi-Banked Compilable DRAM Macro with Direct Write and Programmable Pipeline," ISSCC Dig. Tech. Papers, pp. 204-205, Feb. 2004.
3. J. Safran, A. Leslie, G. Fredeman et al., "A Compact eFUSE Programmable Array Memory for SOI CMOS," Dig. Symp VLSI Circuits, pp. 72-73, Jun. 2007.
4. C. Kothandaraman, S.K. Iyer, S.S. Iyer, "Electrically Programmable Fuse (eFUSE) Using Electromigration in Silicides," Elec. Device Letters, vol. 23, no. 9, pp. 523-525, Sep. 2002.
5. N. Robson, J. Safran, C. Kothandaraman et al., "Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips," Cust. Integ. Circ. Conf., Sep. 2007.