Low-power and high-speed ROM modules for ASIC applications

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 10, 2001, Pages 1516-1523

  Chang, Ching Rong ^a,b   Wang, Jinn Shyan ^a,b   Yang, Cheng Hui ^b  

^a IEEE   (Taiwan)

^b NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

High speed; Low power; NHS PDCMOS; Pseudo footless dynamic CMOS logic decoder; ROM; Selective precharge

Indexed keywords

LOGIC DECODERS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; LOGIC GATES; VLSI CIRCUITS;

ROM;

EID: 0035473375     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.953480     Document Type: Article

References (13)

1. A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM
2. Low-power embedded SRAM with the current-mode write operations
3. Survey of low-power techniques for ROMS
4. High speed compact circuits with CMOS
5. NORA: A racefree dynamic CMOS technique for pipelined logic structures
6. Analysis and design of high-speed and low-power CMOS PLAs
7. A compilable read-only-memory library for ASIC deep-sub-micron applications