A 16 Gb 3-bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB/s write rate

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 195-207

  Li, Yan ^a   Lee, Seungpil ^a   Fong, Yupin ^a   Pan, Feng ^a   Kuo, Tien Chien ^a   Park, Jongmin ^a   Samaddar, Tapan ^a   Nguyen, Hao Thai ^a   Mui, Man L ^a   Htoo, Khin ^a   Kamei, Teruhiko ^a   Higashitani, Masaaki ^a   Yero, Emilio ^a   Kwon, Gyuwan ^a   Kliza, Phil ^a   Wan, Jun ^a   Kaneko, Tetsuya ^b   Maejima, Hiroshi ^b   Shiga, Hitoshi ^b   Hamada, Makoto ^b   Fujita, Norihiro ^b   Kanebako, Kazunori ^b   Tam, Eugene ^a   Koh, Anne ^a   Lu, Iris ^a   Kuo, Calvin Chia Hong ^a   Pham, Trung ^a   Huynh, Jonathan ^a   Nguyen, Qui ^a   Chibvongodze, Hardwell ^a   Watanabe, Mitsuyuki ^a   Oowada, Ken ^a   Shah, Grishma ^a   Woo, Byungki ^a   Gao, Ray ^a   Chan, James ^a   Lan, James ^a   Hong, Patrick ^a   Peng, Liping ^a   Das, Debi ^a   Ghosh, Dhritiman ^a   Kalluru, Vivek ^a   Kulkarni, Sanjay ^a   Cernea, Raul Adrian ^a   Huynh, Sharon ^a   Pantelakis, Dimitris ^a   Wang, Chi Ming ^a   Quader, Khandker ^a   more..

^a SanDisk Corporation   (United States)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

3 bit per cell; 56nm; ABL architecture; All bitline; Bitline control; Cache program; Flash memory; Full sequence; NAND; Source noise cancellation; Wordline control; X3 chip

Indexed keywords

ARCHITECTURE; CACHE MEMORY; CMOS INTEGRATED CIRCUITS; CONCURRENCY CONTROL; SPURIOUS SIGNAL NOISE; TROPOSPHERE;

3-BIT PER CELL; 56NM; ABL ARCHITECTURE; ALL BITLINE; BITLINE CONTROL; CACHE PROGRAM; FULL SEQUENCE; NAND; SOURCE NOISE CANCELLATION; WORDLINE CONTROL; X3 CHIP;

FLASH MEMORY;

EID: 58149250393     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007154     Document Type: Conference Paper

References (8)

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