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Volumn 42, Issue 1, 2007, Pages 219-229

A 56-nm CMOS 99-mm 2 8-Gb multi-level NAND flash memory with 10-MB/s program throughput

(35)  Takeuchi, Ken a,b   Kameda, Yasushi b   Fujimura, Susumu b   Otake, Hiroyuki b   Hosono, Koji b   Shiga, Hitoshi b   Watanabe, Yoshihisa b   Futatsuyama, Takuya b   Shindo, Yoshihiko b   Kojima, Masatsugu b   Iwai, Makoto b   Shirakawa, Masanobu b   Ichige, Masayuki b   Hatakeyama, Kazuo b   Tanaka, Shinichi b   Kamei, Teruhiko c   Fu, Jia Yi c   Cernea, Adi c   Li, Yan c   Higashitani, Masaaki c   more..

a IEEE   (Japan)

Author keywords

Flash memory; High speed programming; Multi level cell; NAND flash memory

Indexed keywords

HIGH SPEED PROGRAMMING; INTEGRATED SEMICONDUCTOR CHIPS; MULTI LEVEL CELL; NAND FLASH MEMORY;

EID: 33846216331     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.888299     Document Type: Article
Times cited : (59)

References (8)
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    • Masuoka, F.1    Momodomi, M.2    Iwata, Y.3    Shirota, R.4
  • 2
    • 0031145164 scopus 로고    scopus 로고
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    • 2 64-Mb NAND flash memory achieving 180 ns/byte effective program speed," IEEE J. Solid-State Circuits, vol. 32, pp. 670-680, 1997.
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    • Kim, J.K.1
  • 3
    • 28144459824 scopus 로고    scopus 로고
    • 2 8 Gb NAND flash memory with 70 nm CMOS technology
    • 2 8 Gb NAND flash memory with 70 nm CMOS technology," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 44-45.
    • (2005) IEEE ISSCC Dig. Tech. Papers , pp. 44-45
    • Hare, T.1
  • 4
    • 28144453513 scopus 로고    scopus 로고
    • A 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology
    • D. S. Byeon et al., "A 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology," in IEEE ISSCC Dig. Tech. Papers, 2005, pp. 46-47.
    • (2005) IEEE ISSCC Dig. Tech. Papers , pp. 46-47
    • Byeon, D.S.1
  • 6
    • 33846227684 scopus 로고    scopus 로고
    • 2 8 Gb multi-level NAND flash memory with 10 MB/sec program throughput
    • 2 8 Gb multi-level NAND flash memory with 10 MB/sec program throughput," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 144-145.
    • (2006) IEEE ISSCC Dig. Tech. Papers , pp. 144-145
    • Takeuchi, K.1
  • 7
    • 0031376620 scopus 로고    scopus 로고
    • A multipage cell architecture for high-speed programming multilevel NAND flash memories
    • K. Takeuchi et al., "A multipage cell architecture for high-speed programming multilevel NAND flash memories," in Symp. VLSI Circuits Dig. Papers, 1997, pp. 67-68.
    • (1997) Symp. VLSI Circuits Dig. Papers , pp. 67-68
    • Takeuchi, K.1
  • 8
    • 20244373743 scopus 로고
    • A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM
    • Y. Iwata et al., "A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM," IEEE J. Solid-State Circuits, vol. 30, pp. 1157-1164, 1995.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.