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Volumn 17, Issue 6, 2009, Pages 758-769

Analysis and reduction of supply noise fluctuations induced by embedded via-programming ROM

Author keywords

Code patterns; Peak current; Read only memory (ROM); Supply noise

Indexed keywords

CODE-PATTERNS; CURRENT PROFILE; DATA PATTERNS; DE-COUPLING CAPACITANCE; PEAK CURRENT; PEAK CURRENTS; PERIPHERAL CIRCUITS; QFN PACKAGE; READ ONLY MEMORY (ROM); READ-ONLY MEMORIES; ROW DECODER; SUPPLY NOISE;

EID: 67349087909     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2006794     Document Type: Article
Times cited : (13)

References (32)
  • 1
    • 0038382898 scopus 로고    scopus 로고
    • Analysis and optimization of power grids
    • May-Jun
    • S. S. Sapatnekar and H. Su, "Analysis and optimization of power grids," IEEE Des. Test Comput., vol. 20, no. 3, pp. 7-15, May-Jun. 2003.
    • (2003) IEEE Des. Test Comput , vol.20 , Issue.3 , pp. 7-15
    • Sapatnekar, S.S.1    Su, H.2
  • 3
    • 0036857246 scopus 로고    scopus 로고
    • Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits
    • Nov
    • M. Badaroglu et al., "Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits," IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1383-1395, Nov. 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.11 , pp. 1383-1395
    • Badaroglu, M.1
  • 4
    • 0035273397 scopus 로고    scopus 로고
    • Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects
    • Mar
    • A. Krstic, Y. M. Jiang, and K. T. Cheng, "Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 20, no. 3, pp. 416-425, Mar. 2001.
    • (2001) IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst , vol.20 , Issue.3 , pp. 416-425
    • Krstic, A.1    Jiang, Y.M.2    Cheng, K.T.3
  • 5
    • 0035391739 scopus 로고    scopus 로고
    • Measurements and analysis of PLL jitter caused by digital switching noise
    • Jul
    • P. Larsson, "Measurements and analysis of PLL jitter caused by digital switching noise," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1113-1119, Jul. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.7 , pp. 1113-1119
    • Larsson, P.1
  • 6
    • 0032665246 scopus 로고    scopus 로고
    • A study of oscillator jitter due to supply and substrate noise
    • Jan
    • F. Herzel and B. Razavi, "A study of oscillator jitter due to supply and substrate noise," IEEE Trans. Circuits Syst. II, Reg. Papers, vol. 46, no. 1, pp. 56-62, Jan. 1999.
    • (1999) IEEE Trans. Circuits Syst. II, Reg. Papers , vol.46 , Issue.1 , pp. 56-62
    • Herzel, F.1    Razavi, B.2
  • 7
    • 2942635715 scopus 로고    scopus 로고
    • Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs
    • Mar
    • M.-F. Chang, K.-A. Wen, and D.-M. Kwai, "Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs," in Proc. IEEE Int. Symp. Quality Electron. Des., Mar. 2004, pp. 297-302.
    • (2004) Proc. IEEE Int. Symp. Quality Electron. Des , pp. 297-302
    • Chang, M.-F.1    Wen, K.-A.2    Kwai, D.-M.3
  • 9
    • 31644438897 scopus 로고    scopus 로고
    • A full code-pattern coverage high-speed embedded ROM using dynamic virtual guardian technique
    • Feb
    • M.-F. Chang, L.-Y. Chiou, and K.-A. Wen, "A full code-pattern coverage high-speed embedded ROM using dynamic virtual guardian technique," IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 496-506, Feb. 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.2 , pp. 496-506
    • Chang, M.-F.1    Chiou, L.-Y.2    Wen, K.-A.3
  • 10
    • 0030684927 scopus 로고    scopus 로고
    • E. de Angel and E. E. Swartzlander, Jr., Survey of low-power techniques for ROMs, in Proc. IEEE Int. Symp. Low Power Electron. Des., Aug. 1997, pp. 18-20.
    • E. de Angel and E. E. Swartzlander, Jr., "Survey of low-power techniques for ROMs," in Proc. IEEE Int. Symp. Low Power Electron. Des., Aug. 1997, pp. 18-20.
  • 12
    • 0035473375 scopus 로고    scopus 로고
    • Low-power and high-speed ROM modules for ASIC applications
    • Oct
    • C.-R. Chang, J.-S. Wang, and C.-H. Yang, "Low-power and high-speed ROM modules for ASIC applications," IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1516-1523, Oct. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.39 , Issue.11 , pp. 1516-1523
    • Chang, C.-R.1    Wang, J.-S.2    Yang, C.-H.3
  • 14
    • 0037390642 scopus 로고    scopus 로고
    • A low-power ROM using charge recycling and charge sharing technique
    • Apr
    • B. D. Yang and L. S. Kim, "A low-power ROM using charge recycling and charge sharing technique," IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 641-653, Apr. 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.4 , pp. 641-653
    • Yang, B.D.1    Kim, L.S.2
  • 15
    • 0031377960 scopus 로고    scopus 로고
    • A 400 Mhz, 144 Kb CMOS ROM macro for an IBM S/390-class microprocessor
    • Oct
    • A. Tuminaro, "A 400 Mhz, 144 Kb CMOS ROM macro for an IBM S/390-class microprocessor," in Proc. IEEE Int. Conf. Comput. Des., Oct. 1997, pp. 253-255.
    • (1997) Proc. IEEE Int. Conf. Comput. Des , pp. 253-255
    • Tuminaro, A.1
  • 16
    • 0031656330 scopus 로고    scopus 로고
    • Compilable read-only-memory library for ASIC deep sub-micron applications
    • Chennai, India, Jan
    • T. Tsang, "Compilable read-only-memory library for ASIC deep sub-micron applications," in Proc. IEEE 11th Int. Conf. VLSI Des., Chennai, India, Jan. 1998, pp. 490-494.
    • (1998) Proc. IEEE 11th Int. Conf. VLSI Des , pp. 490-494
    • Tsang, T.1
  • 17
    • 0036999740 scopus 로고    scopus 로고
    • Inductive properties of high-performance power distribution grids
    • Dec
    • A. V. Mezhiba and E. G. Friedman, "Inductive properties of high-performance power distribution grids," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 6, pp. 762-776, Dec. 2002.
    • (2002) IEEE Trans. Very Large Scale Integr. (VLSI) Syst , vol.10 , Issue.6 , pp. 762-776
    • Mezhiba, A.V.1    Friedman, E.G.2
  • 18
    • 0036179950 scopus 로고    scopus 로고
    • Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
    • Jan
    • S. Zhao, K. Roy, and C. K. Koh, "Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 21, no. 1, pp. 81-92, Jan. 2002.
    • (2002) IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst , vol.21 , Issue.1 , pp. 81-92
    • Zhao, S.1    Roy, K.2    Koh, C.K.3
  • 19
    • 0344089095 scopus 로고    scopus 로고
    • Optimal decoupling capacitor sizing and placement for standard-cell layout designs
    • Apr
    • H. Su, S. S. Sapatnekar, and S. R. Nassif, "Optimal decoupling capacitor sizing and placement for standard-cell layout designs," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 22, no. 4, pp. 428-436, Apr. 2003.
    • (2003) IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst , vol.22 , Issue.4 , pp. 428-436
    • Su, H.1    Sapatnekar, S.S.2    Nassif, S.R.3
  • 20
    • 29244439390 scopus 로고    scopus 로고
    • On-chip power distribution grids with multiple supply voltages for high performance integrated circuits
    • Apr
    • M. Popovich, E. G. Friedman, M. Sotman, and A. Kolodny, "On-chip power distribution grids with multiple supply voltages for high performance integrated circuits," in Proc. 15th ACM Great Lakes Symp. VLSI, Apr. 2005, pp. 2-7.
    • (2005) Proc. 15th ACM Great Lakes Symp. VLSI , pp. 2-7
    • Popovich, M.1    Friedman, E.G.2    Sotman, M.3    Kolodny, A.4
  • 21
    • 33646412351 scopus 로고    scopus 로고
    • Decoupling capacitors for multi-voltage power distribution systems
    • Aug
    • M. Popovich and E. G. Friedman, "Decoupling capacitors for multi-voltage power distribution systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 3, pp. 217-228, Aug. 2006.
    • (2006) IEEE Trans. Very Large Scale Integr. (VLSI) Syst , vol.14 , Issue.3 , pp. 217-228
    • Popovich, M.1    Friedman, E.G.2
  • 23
    • 67349192832 scopus 로고    scopus 로고
    • Synopsys. Inc, Santa Clara, CA, Composite current source (CCS) power technical white paper, ver. 1.0, Nov. 2005
    • Synopsys. Inc., Santa Clara, CA, "Composite current source (CCS) power technical white paper," ver. 1.0, Nov. 2005.
  • 24
    • 67349268023 scopus 로고    scopus 로고
    • Si2 Open Modeling Coalition, Austin, TX, Effective current source model (ECSM) specification, ver. 2.1, Jul. 2006.
    • Si2 Open Modeling Coalition, Austin, TX, "Effective current source model (ECSM) specification," ver. 2.1, Jul. 2006.
  • 25
    • 67349269122 scopus 로고    scopus 로고
    • Datasheet, High performance 1P Sync HD Via23 programmable ROM
    • Virage Logic Corporation, Rev: 1.05.00
    • Virage Logic Corporation, Fremont, CA, "Datasheet, High performance 1P Sync HD Via23 programmable ROM," Rev: 1.05.00, 2004.
    • (2004)
  • 26
    • 67349197473 scopus 로고    scopus 로고
    • Intellectual Property Library Company (IPLib), Hsinchu, Taiwan, Datasheet, synchronous via-programmable ROM compiler, SRCT25-v1, 2002.
    • Intellectual Property Library Company (IPLib), Hsinchu, Taiwan, "Datasheet, synchronous via-programmable ROM compiler," SRCT25-v1, 2002.
  • 27
    • 67349266874 scopus 로고    scopus 로고
    • Hua Hong NEC (HHNEC), Shanghai, China, Datasheet, 0.25 um synchronous ROM compiler, Hua Jie 0.25 um library, 2003.
    • Hua Hong NEC (HHNEC), Shanghai, China, "Datasheet, 0.25 um synchronous ROM compiler," Hua Jie 0.25 um library, 2003.
  • 28
    • 67349274020 scopus 로고    scopus 로고
    • Siliconware Precision Industries Co., Taichung, Taiwan, QFN64 electrical characterization report, no. RES040406, Feb. 2004.
    • Siliconware Precision Industries Co., Taichung, Taiwan, "QFN64 electrical characterization report," no. RES040406, Feb. 2004.
  • 29
    • 0032136312 scopus 로고    scopus 로고
    • Interconnect and circuit modeling techniques for full-chip power supply noise analysis
    • Aug
    • H. H. Chen and J. S. Neely, "Interconnect and circuit modeling techniques for full-chip power supply noise analysis," IEEE Trans. Component, Packag. Manuf. Technol.-Pt. B, vol. 21, no. 3, pp. 209-215, Aug. 1998.
    • (1998) IEEE Trans. Component, Packag. Manuf. Technol.-Pt. B , vol.21 , Issue.3 , pp. 209-215
    • Chen, H.H.1    Neely, J.S.2
  • 31
    • 0035472466 scopus 로고    scopus 로고
    • Fast low-power decoders for RAMs
    • Oct
    • B. S. Amrutur and M. A. Horowitz, "Fast low-power decoders for RAMs," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1506-1515, Oct. 2001.
    • (2001) IEEE J. Solid-State Circuits , vol.36 , Issue.10 , pp. 1506-1515
    • Amrutur, B.S.1    Horowitz, M.A.2
  • 32
    • 34047110771 scopus 로고    scopus 로고
    • Crosstalk-insensitive via-ROMs using content-aware design framework
    • Jun
    • M.-F. Chang, L.-Y. Chiou, and K.-A. Wen, "Crosstalk-insensitive via-ROMs using content-aware design framework," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 6, pp. 443-447, Jun. 2006.
    • (2006) IEEE Trans. Circuits Syst. II, Exp. Briefs , vol.53 , Issue.6 , pp. 443-447
    • Chang, M.-F.1    Chiou, L.-Y.2    Wen, K.-A.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.